EPP v1.9
Eppmodule
//below is the code for EPP module .
module epp_port (send_info,sent_info,write,data_strobe,resetport,
addr_strobe, interrupt,wait_sig,
spare1,recieved_info,
data_send_reg,addr_send_reg,
data_store_reg,
addr_store_reg,spare2,spare3,
data,reset,clock,oe,spare4,testwaitin,testwaitout
);
output testwaitin;
output testwaitout;
input[1:0] send_info;
output[1:0] sent_info;
input spare4;
output oe;
inout[7:0] data;
input[7:0] data_send_reg;
input[7:0] addr_send_reg;
output[7:0] data_store_reg;
output[7:0] addr_store_reg;
output[1:0] recieved_info;
// input data_
input write;
input data_strobe;
input resetport;
input addr_strobe;
output interrupt;
output wait_sig;
output spare1;
output spare2;
output spare3;
input reset;
input clock;
reg[1:0] sent_info;
reg interrupt;
reg wait_sig;
reg spare1;
reg spare2;
reg spare3;
// reg data_out;
reg[2:0] state;
//new entry
reg[7:0] data_send_reg1;
reg[7:0] addr_send_reg1;
reg[1:0] recieved_info;
reg[7:0] data_store_reg;
reg[7:0] addr_store_reg;
// reg data_send_reg;
// reg addr_send_reg;
// reg[5:0] counter;
parameter s1=3'b000;
parameter s2=3'b001;
parameter s3=3'b010;
parameter s4=3'b011;
parameter s5=3'b100;
parameter s6=3'b101;
parameter s7=3'b110;
parameter s8=3'b111;
//using spare1=0 to send data & using spare1=1 to send address
/*
inout[1:0] send_info;
inout[7:0] data;
*/
reg[1:0] set;
reg[7:0] data_value;
assign oe=(set[0] | set[1]);
assign data[0]=(set==2'b00) ? 1'bz : data_value[0];
assign data[1]=(set==2'b00) ? 1'bz : data_value[1];
assign data[2]=(set==2'b00) ? 1'bz : data_value[2];
assign data[3]=(set==2'b00) ? 1'bz : data_value[3];
assign data[4]=(set==2'b00) ? 1'bz : data_value[4];
assign data[5]=(set==2'b00) ? 1'bz : data_value[5];
assign data[6]=(set==2'b00) ? 1'bz : data_value[6];
assign data[7]=(set==2'b00) ? 1'bz : data_value[7];
reg testwaitin,testwaitout;
always@(posedge clock or posedge reset)begin
if(reset)
begin
testwaitin
testwaitout
set
interrupt
wait_sig
spare1
spare2
spare3
state
recieved_info
sent_info
data_value
data_store_reg
addr_store_reg
end //end of if (reset statement
else
begin
if(sent_info==2'b00)
begin
// interrupt
sent_info
spare1
spare2
// spare3
end
else if(sent_info==2'b01)
begin
//interrupt
spare1
spare2
// spare3
data_send_reg1[7:0]
end
else if(sent_info==2'b10)
begin
// interrupt
spare1
spare2
// spare3
addr_send_reg1[7:0]
end
else begin
// interrupt
// spare1
data_send_reg1[7:0]
addr_send_reg1[7:0]
spare1
spare2
// spare3
// interrupt
end
if(spare4==1'b0)begin spare3
case(state)
3'b000: //neutral state
begin
if(resetport==1'b0)begin
set
sent_info
recieved_info
interrupt
wait_sig
spare1
spare2
spare3
state
data_value
end
else begin
if( data_strobe==1'b0 || addr_strobe==1'b0)
begin
if(data_strobe==1'b0)
begin
if(write==1'b0)begin
state
spare3
end
else begin
state
spare1
spare2
// data_value[7:0]
// set
// set
// sent_info
end
end
else begin
if(write==1'b0)begin
state
spare3
end
else begin
state
spare1
spare2
// data_value[7:0]
// set
// sent_info
end
end
end
else
state
end
end
3'b001: //reading data state
begin
if(data_strobe==1'b0)
begin
testwaitin
wait_sig
state
data_store_reg[7:0]
end
else
begin
recieved_info
wait_sig
state
end
end
3'b010: //write data state
begin
if(data_strobe==1'b0)begin
data_value[7:0]
set
wait_sig
sent_info
end
else
begin
wait_sig
set
state
end
end
3'b011: //reading address data
begin
if(addr_strobe==1'b0)begin
wait_sig
addr_store_reg[7:0]
// spare3
end
else
begin
testwaitout
recieved_info
wait_sig
state
end
end
3'b100://writing address data
begin
if(addr_strobe==1'b0)begin
data_value[7:0]
set
wait_sig
if(spare2==1'b1 && spare1==1'b1)
sent_info
else sent_info
end
else
begin
wait_sig
set
state
end
end
endcase
end //enf of the else of if(reset) statement
end //end of always statement
endmodule