Ethernet MAC 10/100 Mbps

The clock domain crossing from the mtx_clk_pad_i to wb_clk_i violates the basic rule of syncronous digital design: there is no double-triggering, signal from the mtx-clocked trigger goes through a logic (!) to a wb_clk-clocked trigger.

In addition there is no syncronization logic, it just relies on the fact that wb_clk is much faster then mtx_clk and will always able to latch these signals, but I am sure that if wb_clk will be 50 MHz or less (with mtx_clk being 25 MHz) system behaviour will be unpredictable.