* Ethernet MAC 10/100 Mbps


Name: ethmac
Created: Sep 25, 2001
Updated: Sep 18, 2018
SVN Updated: Feb 14, 2012
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 13 reported / 3 solved
Star46you like it: star it!

Other project properties

Category:Communication controller
Development status:Stable
Additional info:ASIC proven, Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL


The Ethernet MAC (Media Access Control), sublevel within the Data Link Layer of the OSI reference model. This core is designed for implementation of CSMA/CD LAN in accordance with the IEEE 802.3 standards.

The MAC is the portion of ethernet core that handles the CSMA/CD protocol for transmission and reception of frames. It peforms Frame Data Encapsulation and Decapsulation, Frame Transmission, and Frame Reception.

Size is approximately 28k gates (2400 flip-flops).


  • Ethernet Design Document is being written (still under construction) Sep 5th). For downloading the working version see the Download section.
  • Ethernet Core Specification is updated (Sep 4th). For downloading see the Download section.
  • Ethernet Data Sheet (Product Brief) is finished. For downloading see the Download section.


  • All modules are joined together in a complete Ethernet solution. (July 30, 2001).
  • WISHBONE DMA Host interface is finished. (July 20, 2001).
  • Control module is finished. (July 10, 2001).
  • RxEthMAC module is updated (June 27, 2001).
  • TxEthMAC module is updated (June 19, 2001).
  • A MII Management Module is updated (June 02, 2001).
  • WISHBONE master interface is finished. Additional DMA core is not needed any more (February 12, 2002)
  • Address recognition system is finished (February 18, 2002).
  • Ethernet Core tested in HW (March 3, 2002).
  • Ethernet Core running under uCLinux (April 17, 2002)
  • Ethernet Core improved (many bugs fixed). Running on Xess XCV800 board (under uCLinux), ORP board and and on Flextronics Semiconductor board with VirtexE 1600 on it. Tested with ping, tftp and ftp protocols (September 4, 2002).
  • Control frame transmission and reception fixed. (November 22, 2002)
  • Ethernet MAC core was tested on Altera's NIOS board. (January 7, 2003)
  • Ethernet MAC core was updated. Some bugs were fixed. (January 30, 2003)
  • Testbench finished. (January 30, 2003)
  • Ethernet MAC core was updated. Some bugs were fixed. (April 30, 2004)
  • Added support for simulation with Icarus Verilog (July 2011)

The IP core has been chosen by Flextronics Semiconductor, proven in FPGA technology and integrated into a Flextronics' design. Flextronics can offer commercial design services to companies that want to use this IP in their products - for more information fill out this questionnaire.