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* Ethernet MAC 10/100 Mbps

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Test MAC FULL DUPLEX TRANSMIT TEST stuck with Iteration limit error #12
Open Juzujka opened this issue almost 6 years ago
Juzujka commented almost 6 years ago

Test was run on Modelsim Intel (Altera) FPGA Starter Edition 10.5b

Test run to

MAC FULL DUPLEX TRANSMIT TEST

...

Time: 116878335

TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )

** Error (suppressible): (vsim-3601) Iteration limit 5000 reached at time 116878669 ns.

and test stuck here

Test with Icarus finished with

END of SIMULATION WARNING: ../bench/verilog/tb_ethernet.v:539: invalid file descriptor/MCD (0x1e) given to $fclose.

peio commented almost 2 years ago

The simulator enters into a loop and reach iteration limit. Solution: add a #1; delay in task set_tx_packet, line 22884 in tb_ethernet.v file.

for(i=.... begin wb_slave.wr_mem(.... sd = sd + 4; #1; end ....


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