OpenCores
Username:
Password:

Remember me
Register

Browse

5x4Gbps CRC generator designed with standard cells

Issue List
synthesis error #1
Closed jainendra opened this issue over 11 years ago
jainendra commented over 11 years ago

hello, i am not able to synthesize your code in xilinx ise 13.2,multiple errors are there. kindly clarify the same.

trueno closed this over 11 years ago
trueno commented over 11 years ago

Code is for AMS0.35, not for Xilinx or any other FPGA.

Assignee
No one
Labels
Request
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.