FPU Double VHDL

In RTL simulation the operation below shows an one-cycle invalid result while ready goes hide. See picture.

        enable <= '1';
        opa <= "0000000011110001100011100011101110011011001101110100000101101001";
        opb <= "0011111010001010110101111111001010011010101111001010111101001000";
        fpu_op <= "010";
        rmode <= "00";
        getready(clk,ready,check_en);
        enable <= '0';
        edges(false,clk,2);
        --Output:8.000000000000074e-311

Changing the number of multiply cycles to 25 Vs 24 initially made the fix.