lundgren, david

FPU Double VHDL

In RTL simulation the operation below shows an one-cycle invalid result while ready goes hide. See picture.  



```
        enable <= '1';
        opa <= "0000000011110001100011100011101110011011001101110100000101101001";
        opb <= "0011111010001010110101111111001010011010101111001010111101001000";
        fpu_op <= "010";
        rmode <= "00";
        getready(clk,ready,check_en);
        enable <= '0';
        edges(false,clk,2);
        --Output:8.000000000000074e-311
````

late result on some operations

for float640_add the following two numbers:

fff8000...00
7ff8000...00

out_fp = fff8... (yours)

softfloat= 7ff8


Please contact jlong@eecs.berkeley.edu for equivalence checking between soft float.c and RTL implementation of FPU

aNaN vs qNaN

If you add the following 2 numbers together:

000..08000
c0200...000

The result is both c02000...00

But the soft float raised an inexact flag, while fpu_double does not.


If you want FPU equivalence checking with soft float library, please contact jlong@eecs.berkeley.edu

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FPU Double VHDL