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CORDIC delay off by one clock #3
Closed cowkleaver opened this issue about 15 years ago
cowkleaver commented about 15 years ago

Files affected:

gh_CORDIC_rotation gh_CORDIC_vectoring gh_r_2_polar gh_r_2_polar_a

There appears to be either a) an extra clock cycle delay in delay elements of the r_2_polar entities or b) tapping x_out one clock cycle too early in the CORDIC modules X(iterations-1) instead of X(iterations)

The effect of this is that the phase appears to be mapped to the wrong quadrant for some inputs.

As a first pass, I went through the r_2_polar modules and replaced every instance of iterations with iterations-1 except for the generic into the CORDIC_rotation. This seems to cure the symptom, but I'm not sure if the rotation should be tapping x_out off of iterations-1 or iterations...

If there is a way to get the files to you I can show you what I changed.

Once it is determined where the error lies, I can submit a polar_2_r module that I cobbled together in the pattern of r_2_polar.

hlefevre was assigned about 15 years ago
hlefevre commented about 15 years ago

You are correct. The indexing for dXLY, dXS, and dYS in defining the mode signal should be (iterations-1).

This is an error in the gh_r_2_polar.vhd, gh_r_2_polar_a.vhd, and gh_r_2_polar_28.vhd files.

Unfortunately, the changes opencores.org made to the web suite make it hard to upload the corrected files...

hlefevre closed this about 15 years ago

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hlefevre
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