Hardware Assisted IEEE 1588 IP Core

Can the period_adj be negative value (2's complement) and adjust timer backwards?

If yes, is the following line in rtc.v always true?

time_adj_08n_32f <= time_adj39: 0 + {16'd0, time_adj_00n_24f}; // add the delta

Thanks, Frank

time_adj_08n_32f <= time_adj39: 0 + {16'd0, time_adj_00n_24f}; // add the delta

Yes, period_adj can be negative value. And its effect is to slow down (set backwards) the timer if time_adj=period_fix+period_adj>=0.

However, when time_adj=period_fix+period_adj<0, the negative time_adj is added to time_adj_08n_32f as a big positive value, advancing the time rather than set back the time as expected.

The latest unit test of RTC in /sim/rtc shows both cases.

So this is a bug if this circuit is intended to set the time backwards with a negative value whose absolute value is larger than period_fix. So It is a limitation if this circuit is intended to slow down the time with a negative value whose absolute value is less than or equal to period_fix.

Then it is better to write in the OPERATION document (which is in progress) how this circuit works along with its limitation.

Yes, period_adj can be negative value. And its effect is to slow down (set backwards) the timer if time_adj=period_fix+period_adj>=0.

However, when time_adj=period_fix+period_adj<0, the time_adj is added to time_acc_30n_08f as a big positive value rather than expected negative value. The actual effect is to advance the timer with a leap.

The latest unit test of RTC in sim/rtc shows both cases.

However, when time_adj=period_fix+period_adj is negative, the actual effect is to advance the time_acc_30n_08f with a big leap, rather than set it backwards.

The newly added unit test of RTC in sim/rtc shows this effect.

This bug/limitation is fixed in version 69. The negative sign of signal time_adj_08n_32f is preserved with signal time_adj_22b_08n_08f.