HD63701 compatible core
Project maintainers
Details
Name: hd63701
Created: Dec 20, 2013
Updated: Feb 15, 2014
SVN Updated: Feb 15, 2014
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Dec 20, 2013
Updated: Feb 15, 2014
SVN Updated: Feb 15, 2014
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties
Category:Processor
Language:Verilog
Development status:Planning
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Planning
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
This project provides a synthesizable IP core compatible with HITACHI HD63701 processors.
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