HDLC controller

The documentation available for this IP CORE is not actualized (do not correspond with the latest version of the VHDL code)

Agreed. The documents state that the Wishbone data in and out is 8 bits wide as are all internal registers. The source code has 32 bit data in and out, and the FIFO registers are 32 bit wide.

This also causes a restriction in that transmit data length must always be on 32 bit boundaries.