Khatib, Jamil

HDLC controller

The bit order for the CRC appears to be reversed.  The first CRC bit should be the first bit transmitted, which is the lsb of each byte.  The CRC package being used (PCK_CRC16_D8.vhd) treats the msb as the first serial bit, but the data is not bit-reversed prior to calling this CRC function.

CRC bit order appears to be incorrect

How can this module be Q.921 compliant, given that this module may be interacting with another implementation that has no requirement to be byte aligned?

Q.921 compliance

How can this module be Q.921 compliant, given that this module may be interacting with another implementation that has no requirement to be byte aligned?

Am I missing something?

Thanks.

The documentation available for this IP CORE is not actualized (do not correspond with the latest version of the VHDL code)

Docummentation Issues

Why don't work 	links:
 http://opencores.org/?do=svnget&type=tar&project=hdlc&file=memory_cores2	(Memory module needed for buffers)?
http://opencores.org/?do=svnget&type=tar&project=hdlc&file=%2Ftrunk%2FCODE     (HDLC code)

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HDLC controller