HDLC controller

How can this module be Q.921 compliant, given that this module may be interacting with another implementation that has no requirement to be byte aligned?

Other hardware / software HDLC framers for Q.921 do not maintain byte alignment. Many communication test equipment vendor's implementation also do not. If this design forces one to always have data padded so that the flag remains byte aligned, how can this be claimed to be compliant?

Perhaps I am missing something.

Admittedly, I have not read through your project very far, but this seems to be a rather big problem if I understand how your framer is designed.

Thanks.