maxim33

I2C slave for data transfer

## Status

\- Tested & verified with Altera FPGA.  

## Features

\- No external clock needed  
\- Easy converted to sma-bus adding a time-out WachDog.  
\- 3 individual addresses and data busses.  
\- 7 bit addressing mode  
\- external Reset  

## Description

This is the first version of a simple I2C slave for 8 bit data transfer written in Verilog.  
Two pull-up resitors needed for SDA and SCL lines.  
Any comment and further elaboration is welcomed.


<h2 id="status">Status</h2>
<p>- Tested &amp; verified with Altera FPGA.<br />
</p>
<h2 id="features">Features</h2>
<p>- No external clock needed<br />
  - Easy converted to sma-bus adding a time-out WachDog.<br />
- 3 individual addresses and data busses.<br />
- 7 bit addressing mode<br />
- external Reset<br />
</p>
<h2 id="description">Description</h2>
<p>This is the first version of a simple I2C slave for 8 bit data transfer written in Verilog. <br />
Two pull-up resitors needed for SDA and SCL lines.<br />
Any comment and further elaboration is welcomed.</p>


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I2C slave for data transfer

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