Thanks for making the core. This is just some feedback. I am using multiple devices. The i2c slave core works ok by itself. However, I have a large amount of other traffic on the i2c bus, and the i2c slave begins malfunctioning when I allow other i2c traffic. Currently, I have to hold the i2c slave core in reset when I'm not using it for it to work. I have not done any serious troubleshooting to see exactly why/when/where it fails...
Even I found the same problem when I tried to access I2c slave core running in my FPGA. The master (Processor) which is hosting, has the single I2C bus shared between two I2C devices and I have connected the FPGA as a slave on the same bus.
When the master broadcasts the address ranging from 0x3 to 0x77, only my device is getting recognized which has a slave address of 0x33. All the other devices are not visible from the master end.
Please, someone help in solving out this issue.
We have tested this core and didn't have this problem. All devices on the bus are working.
We replaced this line
assign sda = (sdaOut == 1'b0) ? 1'b0 : 1'bz;
with the corresponding FPGA primitive, like (take Xilinx 7 series as an example)
IOBUF sda_buf(.I(sdaOut), .O(sdaIn), .T(sdaOut), .IO(sda));