I2C Multiple Bus Controller

I use Isim to simulate the project,report fatal err for package test.

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A part of Isim report:

Compiling package test FATAL_ERROR:Simulator:CompilerAssert.h:40:1.67 - Internal Compiler Error in file ../src/VhdlExpr.cpp at line 8186 For technical support on this issue, please visit http://www.xilinx.com/support.

Thank you for your report. I've removed some unneeded stuff from the 'test.vhd' package. Now ISim should compile it fine. Also, I've improved testbenches for better ISim support (there was an issue related to passing parameters to Verilog modules from VHDL structure).

Nice!Passing data from VHDL to verilog looks dangerous.