JPEG Encoder Verilog

i have downloaded JPEG Encoder Verilog IP Core frm www.opencores.org. i need the simulation results screen shots . could u plz provide me these. thanx for the ip core

wen i am simulating the code in xilinx 9.2i. it has 2 errors stating

1) work/jpeg_top_tb is not compiled properly. Please recompile work/jpeg_top_tb in file "C:/Xilinx92i/huff/jpeg_top_TB.v" without -incremental option. 2) Failed when handling dependencies for module jpeg_top_tb