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Details

Name: jpegencode
Created: Nov 15, 2009
Updated: Mar 17, 2012
SVN Updated: Feb 15, 2010
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 2 reported / 0 solved
Star6you like it: star it!

Other project properties

Category:Video controller
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

This core takes as an input the red, green, and blue pixel values, like from a tiff image file, and creates the JPEG bitstream necessary to build a jpeg image. The core was written in generic, regular Verilog code that can be targeted to any FPGA. The core does not rely on any proprietary IP cores, instead all of the functions required to implement the JPEG encoder are written in Verilog and the code is entirely self-contained. This core has been simulated on many raw images with different quantization and Huffman tables.