Automatic latency equalizer for pipelined designs implemented in VHDL
News
| Dec 16, 2018 | corrected paper URLs | Zabolotny, Wojciech |
| Oct 2, 2016 | added reference to the new paper | Zabolotny, Wojciech |
| Oct 4, 2015 | Added reference to the Xilinx Sync Block as the possible prior art solution | Zabolotny, Wojciech |
| Sep 29, 2015 | Added link to the paper describing the method | Zabolotny, Wojciech |
| Sep 27, 2015 | Corrected typo | Zabolotny, Wojciech |
| Sep 25, 2015 | fixed typo | Zabolotny, Wojciech |
| Sep 25, 2015 | Entered initial version of the description of the project | Zabolotny, Wojciech |
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