Automatic latency equalizer for pipelined designs implemented in VHDL

Dec 16, 2018corrected paper URLsZabolotny, Wojciech
Oct 2, 2016added reference to the new paperZabolotny, Wojciech
Oct 4, 2015Added reference to the Xilinx Sync Block as the possible prior art solutionZabolotny, Wojciech
Sep 29, 2015Added link to the paper describing the methodZabolotny, Wojciech
Sep 27, 2015Corrected typoZabolotny, Wojciech
Sep 25, 2015fixed typoZabolotny, Wojciech
Sep 25, 2015Entered initial version of the description of the projectZabolotny, Wojciech