Lightweight 8051 compatible CPU

Hi, i think that clr ACC.bit and set ACC.bit instructions doesn't work. I use them in a bench and accu is not modified.

Perhaps because in ALU the last entry of acc_input mux is alu_result instead of result_internal which contains the bitfield_result ?.

Thanks for this great core.

This bug has caught me in the middle of a transnational move and I don't know when I will be a ble to work on it.

I will look into it ASAP.

Implemented the fix suggested by Stephane Bouyat and it worked at first trial. Apparently it was just a silly oversight in the ACC writeback path and it doesn´t look like a nasty, fundamental bug.

Actually, it took much more effort to hack the VHDL logging code so that the log matches the SW simulator´s for instruction JBC.

As of revision 26, the core has been tested by the cpu_test simulation TB and on the Dhrystone demo on a DE-1 board so I am closing the bug.

Thanks a lot to the submitter (& fixer)!