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Name: lpu
Created: Jan 30, 2002
Updated: Feb 6, 2002
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Development status:Planning
Additional info:
WishBone compliant: No
WishBone version: n/a


This is a design that mixes processor and memory on a single chip. There are a bunch of operations surrounded by buffers. A central unit tells the data where to go. The operations work on data in certain buffers. Operations are performed by moving the data into the proper buffer. It described in much more detail in the specificaiton attatched at the bottom. I'm working on a C++ model right now.

Design Flow

- Create preliminary spec.
- Create C++ model
- Create code to convert x86 commands to native commands
- Simulate operation of chip
- Optimize C++ model
- Convert Model to SystemC
- Extend SystemC to handle asyncronus logic
- ...


- Created Preliminary Spec.
- Working on C++ model