Memory sizer
This page contains files uploaded to the old opencores website as well as images and documents intended for use on other pages in this project. If you want to download this project or browse its svn, you can do so at the overview-page.
| Date | File | Description |
| 2001-12-19 21:41 | b10_safe_12_18_01_dual_path.zip | This file contains an example of the memory_sizer_dual_path module in use. It has separate byte reversal and byte steering logic for both reads and writes. It consumes about 300 Xilinx Virtex slices and it has been tested at 25 MHz. (The synthesis tools reported about 10 MHz maximum usable clock frequency, but that was without any timing constraints at all. I didn't want to take the time to synthesize with constraints, because it makes my tools "dog-slow." Instead, I just figured that the "critical path" found by the tool was a false one, and decided to test it at 25 MHz. It worked just fine.) DPRAMs are used, so that the operation of the module can be verified (by looking at the contents of the same memory on the other port of the dual ported RAM. |
| 2001-12-19 21:40 | b10_safe_12_18_01_single_path.zip | This file contains an example of the memory_sizer module in use. It uses tri-state buffers to switch buses, so it re-uses the same byte reversal and byte steering logic for both reads and writes. It consumes about 200 Xilinx Virtex slices. It has been tested at 12.5 MHz. (The writing works well even at 25 MHz, but the read operation would not operate that fast on my Xilinx XC2S200...) DPRAMs are used, so that the operation of the module can be verified (by looking at the contents of the same memory on the other port of the dual ported RAM.) |
| 2001-12-19 21:37 | memory_sizer_dual_path.v | This file contains the memory_sizer_dual_path Verilog code. |
| 2001-12-19 21:35 | memory_sizer.v | This file contains the memory_sizer module Verilog code. |
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