Description

This repository contains a high-reliability, silicon-proven MIL-STD-1553B compliant Intellectual Property (IP) core designed specifically for mission-critical aerospace and defense applications. The core features a highly modular architecture providing a complete, single-chip solution for Bus Controller (BC), Remote Terminal (RT), and Bus Monitor (BM) functionalities. Integrated with standard AMBA interfaces, it ensures seamless system integration into modern system-on-chip (SoC) and FPGA topologies.

Key Features

• Full Compliance: Fully compliant with MIL-STD-1553B Notice 2 and STANAG 3838 requirements.
• Multi-Function Operation: Supports simultaneous or independent operation of Bus Controller (BC), Remote Terminal (RT), and Bus Monitor (BM/MT).
• Host Interface: Native high-performance AMBA AXI4-Lite / APB host interface for register configuration and DMA memory-mapped access.
• Physical Layer Integration: Built-in Manchester II encoder/decoder with clock recovery logic optimized for dual-redundant bus channels.
• Fault Injection: Advanced error injection and detection engine for thorough protocol validation and system diagnostic testing.
• Highly Configurable: Modular design allows stripping unused roles (e.g., BM-only or RT-only configurations) to optimize silicon area/LUT utilization.

System Architecture

       +-----------------------------------------------------------+

       |                     AMBA AXI4 / APB Bus                   |
       +------------------------------+----------------------------+
                                      |
                                      v
       +-----------------------------------------------------------+

       |                     Host Interface                        |
       |             (Registers, FIFO, Configuration)              |
       +------------------------------+----------------------------+
                                      |
                                      v
       +-----------------------------------------------------------+

       |               Protocol Execution Engine                   |
       |      +-----------------+--------+-----------------+       |
       |      | Bus Controller  | Remote |  Bus Monitor    |       |
       |      |     (BC)        | Terminal (RT)  (BM)      |       |
       +------+-----------------+--------+-----------------+-------+
                                      |
                                      v
       +-----------------------------------------------------------+

       |            Manchester II Encoder / Decoder                |
       +--------------+------------------------------+-------------+

                      |                              |
                      v                              v
              +---------------+              +---------------+

              |   Channel A   |              |   Channel B   |
              +---------------+              +---------------+

The url of the svn repository is: https://opencores.org/websvn/listing/mil_std_1553b_core/mil_std_1553b_core