philippe

Serial Uart

## Description

Design in VHDL:  
This UART is able to Transmit/Receive bytes in the configuration:  
1 start bit - no parity - 1 stop bit.  
It can be commanded by a microcontroller, or by other IP core.  
It is not suited to interface a modem as there is no control handshaking (CTS/RTS).  
It does'nt contain FIFO for emit/receive.

## Features

• WISHBONE interface in 8-bit data bus  
• Two clock: one for wishbone interface, one for RS232 bitstream generation  
• Baudrate divisor from 1 to 65536 (generic parameter set at integration time)

## Synthesis results

Xilinx:  
• Spartan: XCS10-TQ144-4: 71 flip-flop  
• Spartan-II: XC2S15-CS144-6: 153BELs@107MHz

## Status

Operational


<h2 id="description">Description</h2>
<p>Design in VHDL:<br />
This UART is able to Transmit/Receive bytes in the configuration:<br />
1 start bit - no parity - 1 stop bit.<br />
It can be commanded by a microcontroller, or by other IP core.<br />
It is not suited to interface a modem as there is no control handshaking (CTS/RTS).<br />
It does'nt contain FIFO for emit/receive.</p>
<h2 id="features">Features</h2>
<p>• WISHBONE interface in 8-bit data bus<br />
• Two clock: one for wishbone interface, one for RS232 bitstream generation<br />
• Baudrate divisor from 1 to 65536 (generic parameter set at integration time)</p>
<h2 id="synthesis-results">Synthesis results</h2>
<p>Xilinx:<br />
• Spartan:    XCS10-TQ144-4:  71 flip-flop<br />
• Spartan-II: XC2S15-CS144-6: 153BELs@107MHz</p>
<h2 id="status">Status</h2>
<p>Operational</p>


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Serial Uart

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