ocmips

Pipeline Description

Ocmips is pipelined with six stages, that is

IF(instruction fetch ): PC is updated dependent on whether branch occured or whether multiple clock instructions such as "mult div etc." is executed.

ID(instruction decode ): In ID stage, instruction from IF stage is given to instruction decoder in which every instruction is decoded into micro instructions, for example, instruction type(R-type, I-type, J-type or B-type), memory operations( read or write, byte or word , etc), destination register, whether write back, etc.

OP(alu operand ): In OP stage, regfile is instantiated, data is read or written to regfile, and more importantly, forward logic comes here. Forwarding signal is given for use in EX stage.

EX(excute instruction) : In this stage, firstly, two alu operands are selected depending on forwarding signals and instruction type, and then they are given to ALU module to be operated. Different instruction has defferent ALU operation which determined by micro instructions decoded in ID stage. As refered to multiple clock instructions(multiply and divide), a wait signal is asserted to Next PC logic, that is, pipeline is stalled until wait is deasserted.

MEM(memroy operation) : Memory related signals including "addr, din, we, cs(stb)" is given in this stage, in fact, these signals are given after EX stage, because they are combitional logic. All the memory operation's protocol in ocmips is compatible with Xilinx's block memory.

WB(write back) : Data are written back to regfile in this stage, they selected form two source, one is ALU's output, the other is from data memory's data out pin.

Features

- feature1
- feature1.1
-feature1.2
-feature2

Status

- status1
- status2

Files Description

There are three directory on top.

1) ./nocache_nobpb

./nocache_nobpb/sim----Modelsim simulation directory

./nocache_nobpb/src----Verilog source file
ALU.v----MIPS ALU
BLKMEMSP_V6.2----Xilinx Block Memory primitive
code.v---- 4KByte Code memory
Control.v---- Instruction decoder
data.v---- 8KByte Data memory
GenPc.v---- Next PC logic
LED.v---- Dynamic display
Memory.v---- Data memory and code memory are included in this module
MulDiv.v ---- Multiply and Divider
Ocmips.v ---- Top module of ocmips
PipeBack.v ---- Write Back stage
PipeDec.v ---- ID stage
PipeExe.v ---- EX stage
PipeFet.v ---- IF stage
PipeMem.v ---- MEM stage
PipeOp.v ---- OP stage
RegFile.v ---- Register File
TestTop.v ---- Top testbench file for fpga environment
TestOcmips.v ---- Top testbench file for ocmips
Top.v ---- Top module for fpga environment
uart.v ---- UART transmit module

./nocache_nobpb/syn----Synthesis directory
(Xilinx core generator project for code memory and data memory, Synplify project and Xilinx ISE project for ocmips, are all in this directory)

2) ./test
Test program including assemblly and c are given in this directory. Every test directory contains a Windows batch command file which used to assemble or compile test program.

3) ./tools
GCC cross tool chain is given in this directory. Have depicted in last section, compile c program using Windows batch command file is NOT surported. You'd better use make file in Linux or Cygwin environment

Simulation Environment

Description of TestOcmips.v :

In this file, there are some monitors for debug simulation

1) mem.log, data memory bus monitor

2) reg.log, register file bus monitor

3) console.log, GPIO and UART Transmit monitor

These monitors print messages to related file, user may observe the value of bus in these files.

A macro called "UART" may be defined or undefined both in verilog soure file "defines.v" and C test programs. This macro determin how the function "print_char()" is implemented.

If it is defined, "'print_char()" will print data to uart transmitter' data register(0x80000010), it may cost a very long time to simulate the core, because the baudrate is so low.result can be checked in console.log

If it is NOT defined, "print_char()" will print data to 0x80000004, you may see that the simulation ended very soon, and also, result can be checked in console.log

FPGA Verification Environment

In FPGA verification environment, the top module is Top.v, and the testbench is TestTop.v.

The only valuable external pin is UART's txd and rxd serial line. Results of C test programs are all transmitted to PC's super terminal through UART. I test it use "count.c" program form OpenCores' Plasma project.

Here is an example :

#define UART

#ifdef UART
#define REG_UART_TXEPTY *(volatile unsigned char *)(0x80000011)
#define REG_UART_TXDATA *(volatile unsigned char *)(0x80000010)
#endif

void print_char(char data)
{
#ifndef UART
__asm__ __volatile__(
"la $16,0x80000010\n\t"
"sb %0,0($16)\n\t"
:
: "r"(data)
: "$16"
);
#else
unsigned char tmp;
tmp = REG_UART_TXEPTY;
while(!tmp){
tmp = REG_UART_TXEPTY;
}
REG_UART_TXDATA = data;
#endif
}

Address Map

4k-byte inst rom : 0x0000_0000~0x0000_0fff

8k-byte uncached data ram : 0x0004_0000~0x0004_1fff

32-bit GPIO ,addr = 0x80000000 (function "print_int()" will print integer to this addr, 0x80000004 is recognized as single byte integer when the core is simulated)

UART transmitter, 0x80000013, 0x80000012, 0x80000011(TRE), 0x80000010(TDATA)(function "print_char" will print ASCII character to TDATA register)

IMAGE: thumb_opencores.gif

FILE: thumb_opencores.gif
DESCRIPTION: Block Diagram of OCMIPS

IMAGE: thumb_fpga.gif

FILE: thumb_fpga.gif
DESCRIPTION: Result of Count Test

Known Bugs

I tested ocmips with a lot of assemblly program, and mainly four c program(sort, count, calculate pi, calculate factorial of ten) which adapted from OpenCores' other mips compatible processors. All the program except fac.c works well.

console.log output :

************************************************************
OCMIPS CPU (MIPS32 Compatible)
Designed by Xue Bo, xuebocn@gmail.com
Shanghai, People's Republic of China
processor can be downloaded from www.opencores.com
******************************************************
c(10)=)=0003628800c(10)=

but it should be :

************************************************************
OCMIPS CPU (MIPS32 Compatible)
Designed by Xue Bo, xuebocn@gmail.com
Shanghai, People's Republic of China
This processor can be downloaded from www.opencores.com
******************************************************
fac(10)=0003628800

I think there may be a bug in the analysis of ELF file but not the core's bug, because the value of factorial is quite right, and most importantly, the soft simulator output the same error result as verilog core! Can anyone help to fix it?

IMAGE: thumb_sim.GIF

FILE: thumb_sim.GIF
DESCRIPTION: Soft simulator in C