Open8 uRISC
News
| Oct 5, 2023 | Added a new sample project for the task manager. This project targeted a custom board set from years ago that I still use for development. There are two versions, one for the "serial breakout" and another for the "muxed RAM breakout". This demonstrates the use of generics to let software know which version is running via the version register (slightly misused). This also contains the latest task switcher code, which now makes use of a new core called o8_ts_ioctl. This new core merges the PIT task timer, 16-bit cascaded interrupt controller, and 16-bit IO write qualification register into a single entity, and dramatically simplifies using the task switcher. | jshamlet |
| Oct 5, 2023 | Added some new entities in preparation for a sample project that demonstrates the latest task switching system. These include a watchdog timer and a custom SPI-like interface for a CPLD attached LCD - included so the project will compile. | jshamlet |
| May 18, 2023 | Updated the front page to indicate the primary purpose of the Open8 as a microcontroller platform | jshamlet |
| May 18, 2023 | Added a new set of entities for the Terasic DE0 Nano board's ADC. This includes the ADC interface itself, a 16-channel, 64-deep rolling averager, and memory-mapped buffer. This allows Open8 programs to read any ADC channel with only two LDA instructions, offloading the SPI interface and rolling average calculation to firmware. | jshamlet |
| Jul 16, 2022 | The code janitor finally got after a simple task manager for the Open8. It's not full featured, but it does work. Tasks consists of two functions - an "init" and "exec" function. The rest of the system is autogenerated based on constants and a configuration file. Switching is straight round-robin, though supervisor mode code can (and has in the past) alter the TaskMgr.Next_Task variable to alter priority. The system also allows each task to define up to 5 unique soft-interrupt functions for either guaranteed atomic operations or to create inter-task communication systems (as the task manager does not yet provide for inter-task comms itself) (edited) | jshamlet |
| Jul 13, 2022 | It's never too late to find ancient bugs. This time it was the rarely used SBC instruction, which had a fault in the 2's complement code. The actual problem was failing to add the '1', but I ended up reimplementing with - instead and letting the compiler do that for me. The instruction should no longer be off by one or screw up carry only subtracts. | jshamlet |
| Sep 17, 2021 | The vector interface got a slight overhaul due to lab debugging. I removed the parallel interface, so it is serial only, and it now includes an interlock that requires the ISR to clear a pending flag. This prevents the core from pounding the CPU with interrupts if the sender repeatedly issues packets. It also works with flow control to hold off the sender. While this entire system could have been implemented as a task, this specific project really needed an interrupt based vector receiver, so this is a mildly project-specific core, but it does work quite well. | jshamlet |
| Jun 15, 2021 | Updated the o8_trig_delay entity by: 1) Added a global interrupt enable, 2) Added the ability to trigger on both the pre- and post-arm trigger input 3) Added the ability to read the external input on offset 7 | jshamlet |
| May 5, 2021 | Added new feature descriptions | jshamlet |
| May 4, 2021 | After spending several hours trying to debug a SPI device driver program, I decided to add a generic to make ROL/ROR behave in the more traditional manner. By setting Rotation_Ignores_Carry true, the CPU will now ignore the carry bit entirely for rotations. ROL will now perform Rn(6:0)&Rn(7) => Rn and ROR will perform Rn(0)&Rn(7:1) => Rn. The carry bit is not altered in this modified instruction. Also, PSR_GP4 can now be referred to as PSR_S in the WLA based assembler. It generates the same sub-op as PSR_GP4, and is solely used to make code altering the RSP instruction more descriptive. | jshamlet |
| Apr 16, 2021 | Wrote a "universal" character LCD driver for HD44780 based panels. This removes the auto-initialization code, but introduces a new tunable interface. The init code really only worked well for panels in 8-bit mode anyway, so this isn't a major loss. (edited) | jshamlet |
| Oct 23, 2020 | Replaced the Stack_Xfer_Flag generic with a constant for a few reasons. Chiefly because it allows all of the CPU internal architecture constants to be moved into the actual o8_cpu entity, rather than the Open8_pkg file. It is presently fixed as PSR_GP4, though the constant can be altered. This would impact software that depends on this behavior. | jshamlet |
| Oct 21, 2020 | A bit over 14 years later, and I realized that there was a massive performance penalty in the data path. I have now corrected this, and CPU states that issue the program counter to the data bus now use 2 enumerated signals without altering the .reg field. (edited) | jshamlet |
| Jul 10, 2020 | Fixed an apparently long-standing bug in the auto-increment logic for LDO and LDX. I am amazed this one took so long to discover, but it only affects code where the register pair wraps around xxFF. | jshamlet |
| Jun 10, 2020 | Added the ability to use unsigned offsets for LDO/STO. The default behavior is still signed, as this is a very old design decision. Also, LDO and STO have an additional pipeline stage to allow their offset calculation to be registered before being muxed onto the address bus. This does increase their latency by 1, but it makes the whole core easier to hit higher Fmax with by making all of the address sources registers. Also, while reviewing the generated logic, the ISR_Addr signal was being created as a 16-bit register, even though only the lower 4 bits are modified. The ISR address now hard-wires the upper 12 bits based on the generic, with only the lower 4 bits being driven by logic. | jshamlet |
| May 20, 2020 | Added supervisor mode logic to the CPU model, and write-protection logic to most modules, including the RAM models. This allows for robust memory protection for multitasking applications. | jshamlet |
| Apr 21, 2020 | Updated the sample projects ZIP file with cleaned up versions of the configuration and assembly files. While the assembly still isn't production worthy, the way the constants are defined and referenced to the Open8_cfg.vhd file should be more clear. | jshamlet |
| Apr 18, 2020 | Apparently there has been some confusion on how to use the Open8 in a functioning system. I have uploaded two sample projects which communicate with each other as a demonstration. The assembly programs are test-bed level, and not even close to debugged final code, but the projects do work. | jshamlet |
| Apr 16, 2020 | I finally got tired of copy/pasting the same bits of code every time I instantiated a new peripheral, so I created an OPEN8_BUS_TYPE record that contains all of the common signals from the CPU to a peripheral, including the clock, reset, usec tick, address, write enable, write data, and read enable. The Reset_Level constant was also moved to the package file, since it is now common. The CPU model was updated to take a clock and pll locked signal, and then generate a bus reset signal. It also now contains a microsecond timer to feed the uSec_Tick pulse - as this is a very commonly needed signal. The top-level of my current design is now dramatically simpler, and as a bonus, has an ever so slightly faster fMax. | jshamlet |
| Apr 10, 2020 | The modified RSP (Relocate/Retrieve Stack Pointer) command has been thorougly tested now. I have a very simple task switching kernel hosted on a DE0 Nano board at 100MHz with a 250uS PIT. The design is running four tasks (plus a fifth idle task), where one of the tasks has interrupt priority. (A separate timer can reset the PIT down and insert the test stimulus task as the next task). I'm now satisfied that the HDL changes to the CPU are good. | jshamlet |
| Apr 9, 2020 | The project I'm working on now uses multiple tasks that need to be preemptively multitasked. This exposed a flaw in the system timer model, which didn't handle updates correctly for this case. The system timer and RTC PIT timer models have been updated to properly reset the timer on interval writes. Also, a new compile option for the CPU was added to force interrupts to be sequential, blocking new interrupts if the I-bit is set. Lower priority/interruptable ISRs can clear the I-bit prematurely to avoid blocking higher level interrupts, but this allows non-interruptable ISRs to work without having to mess with the interrupt mask. (which was, itself, potentially interruptable) (edited) | jshamlet |
| Mar 31, 2020 | Cleaned up the code and added back the OPEN8_NULLBUS constant for read data. Also added a new o8 memory-mapped SDLC subsystem that is now stable. As part of the test, the 8-bit LCD interface has had a workout as well. Lastly, the button interrupt code is much more flexible now, with the main debounce code moved to a separate entity and instantiated with generics. | jshamlet |
| Mar 19, 2020 | Regression testing on actual hardware revealed a bug in the RTI/RTS instruction that crept in where the instruction cache wasn't being disabled. This caused intermittent failure to properly decode RTI, often resulting in an RTS, which corrupts the stack after ISRs. This was apparently introduced during the address generation simplification, and has now been fixed. (edited) | jshamlet |
| Mar 18, 2020 | Merged changes from private versions into the public repository. These are mostly comment fixes, but the ceil_log2 function was moved to the package file since it gets used as part of the CPU setup. | jshamlet |
| Mar 16, 2020 | More bug fixes, though they are getting more obscure. This time, it's the SMSK instruction, which, if interrupted, could have effectively executed twice. This isn't a major one, but the CPU now correctly undoes the first execution when interrupted. Also, added back the ability to halt the CPU, except now it works within the context of the instruction decoder. The line will cause the very next instruction to be paused, then go into a holding state until the line is deasserted. This is a lot more easy on the gates than the old clock enable model. | jshamlet |
| Mar 14, 2020 | Added the ability to truly modify the stack for multi-tasking by modifying the RSP instruction to conditionally set and get the SP. Also did some major spring cleaning, fixing some long-standing bugs as well as simplifying the logic enough to drop the LUT count by quite a bit (which helps with Fmax) (edited) | jshamlet |
| Mar 10, 2020 | Modified the RSP instruction to work in both directions (SP->R1:R0 or R1:R0->SP) based on any of the four unused CPU status flags. Also modified the LDX instruction to simplify the address logic. | jshamlet |
| Feb 25, 2020 | Added personal assembler/linker tool chain to the project. | jshamlet |
| Jul 20, 2016 | Added a 4 and 8-bit character LCD interface with optional backlight and contrast DACs. | jshamlet |
| Jan 7, 2016 | Added some useful entities developed for various projects, including an epoch timer/alarm clock, clock state detector, and button interface. | jshamlet |
| Nov 16, 2015 | Added a comment noted that this is a von-neumann style core, where code and data are all placed within the same memory space. | jshamlet |
| Nov 13, 2015 | Fixed issue with carry flag while executing the CMP and SBC instructions. Previous implementation inverted the carry flag behavior improperly. | jshamlet |
| Sep 23, 2013 | Removed superfluous reason for BSD license | jshamlet |
| Sep 18, 2013 | Updated processor model with several bug fixes. | jshamlet |
| Mar 3, 2012 | Revised project information to be more current. | Hays, Kirk |
| Dec 22, 2011 | Modified the WAIT_FOR_INT state to allow the bus to go entirely idle after a WAI instruction | jshamlet |
| Nov 14, 2011 | Open8 tools synchronized with binutils 2.22.51.20111114 | Hays, Kirk |
| Sep 22, 2011 | Checked in new processor model with BRK_Implements_WAI functionality, | jshamlet |
| Sep 21, 2011 | Discussed current usage of model, including BRK_Implements_WAI option still under testing. | jshamlet |
| Aug 29, 2011 | Synchronize binutils/ in the svn tree with gnu dev tree of 2.21.53.20110828. | Hays, Kirk |
| Jul 27, 2011 | Almost done with timing optimizations. In the process, the model has been flattened to a single entity. | jshamlet |
| Jul 27, 2011 | Several blocks have been further optimized. Not much in the way of speed, but the model should be about 2% smaller. | jshamlet |
| Jul 27, 2011 | More bug fixes - interrupts should be 100% functional now. | jshamlet |
| Jun 17, 2011 | Correct the descriptions for GMSK and SMSK instructions in the Open8 Assembly Language Reference | Hays, Kirk |
| Jun 15, 2011 | corrected HTML on project page | Hays, Kirk |
| Jun 15, 2011 | Fixed a couple of bugs in the CPU core related to address corruption | jshamlet |
| Jun 14, 2011 | clr "Clear Accumulator" pseudo-instruction added to binutils | Hays, Kirk |
| Jun 13, 2011 | binutils updated to 20110613 | Hays, Kirk |
| Jun 4, 2011 | Note that binutils checkin will not be complete until Monday, June 6th. | Hays, Kirk |
| Jun 4, 2011 | Announcement of binutils source addition to the Open8 repository. | Hays, Kirk |
| Apr 13, 2011 | Core description updated to clarify that the implementation requires two clock latency for memory and register files. | Hays, Kirk |
| Apr 4, 2011 | Updated Project Status to reflect current status (Hi-Tech compiler no longer available, assembly manual added, GNU binutils close to release) | Hays, Kirk |
| Mar 10, 2011 | Added assembly language reference manual for upcoming binutils release. | Hays, Kirk |
| Jan 25, 2011 | Fixed spelling errors | jshamlet |
| Jan 24, 2011 | SVN updated to reflect fixes of 1/18/2011 - revision 10 is now the latest revision | Hays, Kirk |
| Jan 18, 2011 | Fixed BTT instruction to match actual V8 behavior | jshamlet |
| Sep 11, 2006 | Project started | lampret |
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