OpenCores
News
Mar 31, 2020Cleaned up the code and added back the OPEN8_NULLBUS constant for read data. Also added a new o8 memory-mapped SDLC subsystem that is now stable. As part of the test, the 8-bit LCD interface has had a workout as well. Lastly, the button interrupt code is much more flexible now, with the main debounce code moved to a separate entity and instantiated with generics.jshamlet
Mar 19, 2020Regression testing on actual hardware revealed a bug in the RTI/RSP instruction that crept in where the instruction cache wasn't being disabled. This caused intermittent failure to properly decode RTI, often resulting in an RTS, which corrupts the stack after ISRs. This was apparently introduced during the address generation simplification, and has now been fixed. (edited)jshamlet
Mar 18, 2020Merged changes from private versions into the public repository. These are mostly comment fixes, but the ceil_log2 function was moved to the package file since it gets used as part of the CPU setup.jshamlet
Mar 16, 2020More bug fixes, though they are getting more obscure. This time, it's the SMSK instruction, which, if interrupted, could have effectively executed twice. This isn't a major one, but the CPU now correctly undoes the first execution when interrupted. Also, added back the ability to halt the CPU, except now it works within the context of the instruction decoder. The line will cause the very next instruction to be paused, then go into a holding state until the line is deasserted. This is a lot more easy on the gates than the old clock enable model.jshamlet
Mar 14, 2020Added the ability to truly modify the stack for multi-tasking by modifying the RSP instruction to conditionally set and get the SP. Also did some major spring cleaning, fixing some long-standing bugs as well as simplifying the logic enough to drop the LUT count by quite a bit (which helps with Fmax) (edited)jshamlet
Mar 10, 2020Modified the RSP instruction to work in both directions (SP->R1:R0 or R1:R0->SP) based on any of the four unused CPU status flags. Also modified the LDX instruction to simplify the address logic.jshamlet
Feb 25, 2020Added personal assembler/linker tool chain to the project.jshamlet
Jul 20, 2016Added a 4 and 8-bit character LCD interface with optional backlight and contrast DACs.jshamlet
Jan 7, 2016Added some useful entities developed for various projects, including an epoch timer/alarm clock, clock state detector, and button interface.jshamlet
Nov 16, 2015Added a comment noted that this is a von-neumann style core, where code and data are all placed within the same memory space.jshamlet
Nov 13, 2015Fixed issue with carry flag while executing the CMP and SBC instructions. Previous implementation inverted the carry flag behavior improperly.jshamlet
Sep 23, 2013Removed superfluous reason for BSD licensejshamlet
Sep 18, 2013Updated processor model with several bug fixes.jshamlet
Mar 3, 2012Revised project information to be more current.Hays, Kirk
Dec 22, 2011Modified the WAIT_FOR_INT state to allow the bus to go entirely idle after a WAI instructionjshamlet
Nov 14, 2011Open8 tools synchronized with binutils 2.22.51.20111114Hays, Kirk
Sep 22, 2011Checked in new processor model with BRK_Implements_WAI functionality,jshamlet
Sep 21, 2011Discussed current usage of model, including BRK_Implements_WAI option still under testing.jshamlet
Aug 29, 2011Synchronize binutils/ in the svn tree with gnu dev tree of 2.21.53.20110828.Hays, Kirk
Jul 27, 2011Almost done with timing optimizations. In the process, the model has been flattened to a single entity.jshamlet
Jul 27, 2011Several blocks have been further optimized. Not much in the way of speed, but the model should be about 2% smaller.jshamlet
Jul 27, 2011More bug fixes - interrupts should be 100% functional now.jshamlet
Jun 17, 2011Correct the descriptions for GMSK and SMSK instructions in the Open8 Assembly Language ReferenceHays, Kirk
Jun 15, 2011corrected HTML on project pageHays, Kirk
Jun 15, 2011Fixed a couple of bugs in the CPU core related to address corruptionjshamlet
Jun 14, 2011clr "Clear Accumulator" pseudo-instruction added to binutilsHays, Kirk
Jun 13, 2011binutils updated to 20110613Hays, Kirk
Jun 4, 2011Note that binutils checkin will not be complete until Monday, June 6th.Hays, Kirk
Jun 4, 2011Announcement of binutils source addition to the Open8 repository.Hays, Kirk
Apr 13, 2011Core description updated to clarify that the implementation requires two clock latency for memory and register files.Hays, Kirk
Apr 4, 2011Updated Project Status to reflect current status (Hi-Tech compiler no longer available, assembly manual added, GNU binutils close to release)Hays, Kirk
Mar 10, 2011Added assembly language reference manual for upcoming binutils release.Hays, Kirk
Jan 25, 2011Fixed spelling errorsjshamlet
Jan 24, 2011SVN updated to reflect fixes of 1/18/2011 - revision 10 is now the latest revisionHays, Kirk
Jan 18, 2011Fixed BTT instruction to match actual V8 behaviorjshamlet
Sep 11, 2006Project startedlampret