May 5, 2021Added new feature descriptionsjshamlet
May 4, 2021After spending several hours trying to debug a SPI device driver program, I decided to add a generic to make ROL/ROR behave in the more traditional manner. By setting Rotation_Ignores_Carry true, the CPU will now ignore the carry bit entirely for rotations. ROL will now perform Rn(6:0)&Rn(7) => Rn and ROR will perform Rn(0)&Rn(7:1) => Rn. The carry bit is not altered in this modified instruction. Also, PSR_GP4 can now be referred to as PSR_S in the WLA based assembler. It generates the same sub-op as PSR_GP4, and is solely used to make code altering the RSP instruction more descriptive.jshamlet
Apr 16, 2021Wrote a "universal" character LCD driver for HD44780 based panels. This removes the auto-initialization code, but introduces a new tunable interface. The init code really only worked well for panels in 8-bit mode anyway, so this isn't a major loss. (edited)jshamlet
Oct 23, 2020Replaced the Stack_Xfer_Flag generic with a constant for a few reasons. Chiefly because it allows all of the CPU internal architecture constants to be moved into the actual o8_cpu entity, rather than the Open8_pkg file. It is presently fixed as PSR_GP4, though the constant can be altered. This would impact software that depends on this behavior.jshamlet
Oct 21, 2020A bit over 14 years later, and I realized that there was a massive performance penalty in the data path. I have now corrected this, and CPU states that issue the program counter to the data bus now use 2 enumerated signals without altering the .reg field. (edited)jshamlet
Jul 10, 2020Fixed an apparently long-standing bug in the auto-increment logic for LDO and LDX. I am amazed this one took so long to discover, but it only affects code where the register pair wraps around xxFF.jshamlet
Jun 10, 2020Added the ability to use unsigned offsets for LDO/STO. The default behavior is still signed, as this is a very old design decision. Also, LDO and STO have an additional pipeline stage to allow their offset calculation to be registered before being muxed onto the address bus. This does increase their latency by 1, but it makes the whole core easier to hit higher Fmax with by making all of the address sources registers. Also, while reviewing the generated logic, the ISR_Addr signal was being created as a 16-bit register, even though only the lower 4 bits are modified. The ISR address now hard-wires the upper 12 bits based on the generic, with only the lower 4 bits being driven by logic.jshamlet
May 20, 2020Added supervisor mode logic to the CPU model, and write-protection logic to most modules, including the RAM models. This allows for robust memory protection for multitasking applications.jshamlet
Apr 21, 2020Updated the sample projects ZIP file with cleaned up versions of the configuration and assembly files. While the assembly still isn't production worthy, the way the constants are defined and referenced to the Open8_cfg.vhd file should be more clear.jshamlet
Apr 18, 2020Apparently there has been some confusion on how to use the Open8 in a functioning system. I have uploaded two sample projects which communicate with each other as a demonstration. The assembly programs are test-bed level, and not even close to debugged final code, but the projects do work.jshamlet
Apr 16, 2020I finally got tired of copy/pasting the same bits of code every time I instantiated a new peripheral, so I created an OPEN8_BUS_TYPE record that contains all of the common signals from the CPU to a peripheral, including the clock, reset, usec tick, address, write enable, write data, and read enable. The Reset_Level constant was also moved to the package file, since it is now common. The CPU model was updated to take a clock and pll locked signal, and then generate a bus reset signal. It also now contains a microsecond timer to feed the uSec_Tick pulse - as this is a very commonly needed signal. The top-level of my current design is now dramatically simpler, and as a bonus, has an ever so slightly faster fMax.jshamlet
Apr 10, 2020The modified RSP (Relocate/Retrieve Stack Pointer) command has been thorougly tested now. I have a very simple task switching kernel hosted on a DE0 Nano board at 100MHz with a 250uS PIT. The design is running four tasks (plus a fifth idle task), where one of the tasks has interrupt priority. (A separate timer can reset the PIT down and insert the test stimulus task as the next task). I'm now satisfied that the HDL changes to the CPU are good.jshamlet
Apr 9, 2020The project I'm working on now uses multiple tasks that need to be preemptively multitasked. This exposed a flaw in the system timer model, which didn't handle updates correctly for this case. The system timer and RTC PIT timer models have been updated to properly reset the timer on interval writes. Also, a new compile option for the CPU was added to force interrupts to be sequential, blocking new interrupts if the I-bit is set. Lower priority/interruptable ISRs can clear the I-bit prematurely to avoid blocking higher level interrupts, but this allows non-interruptable ISRs to work without having to mess with the interrupt mask. (which was, itself, potentially interruptable) (edited)jshamlet
Mar 31, 2020Cleaned up the code and added back the OPEN8_NULLBUS constant for read data. Also added a new o8 memory-mapped SDLC subsystem that is now stable. As part of the test, the 8-bit LCD interface has had a workout as well. Lastly, the button interrupt code is much more flexible now, with the main debounce code moved to a separate entity and instantiated with generics.jshamlet
Mar 19, 2020Regression testing on actual hardware revealed a bug in the RTI/RTS instruction that crept in where the instruction cache wasn't being disabled. This caused intermittent failure to properly decode RTI, often resulting in an RTS, which corrupts the stack after ISRs. This was apparently introduced during the address generation simplification, and has now been fixed. (edited)jshamlet
Mar 18, 2020Merged changes from private versions into the public repository. These are mostly comment fixes, but the ceil_log2 function was moved to the package file since it gets used as part of the CPU setup.jshamlet
Mar 16, 2020More bug fixes, though they are getting more obscure. This time, it's the SMSK instruction, which, if interrupted, could have effectively executed twice. This isn't a major one, but the CPU now correctly undoes the first execution when interrupted. Also, added back the ability to halt the CPU, except now it works within the context of the instruction decoder. The line will cause the very next instruction to be paused, then go into a holding state until the line is deasserted. This is a lot more easy on the gates than the old clock enable model.jshamlet
Mar 14, 2020Added the ability to truly modify the stack for multi-tasking by modifying the RSP instruction to conditionally set and get the SP. Also did some major spring cleaning, fixing some long-standing bugs as well as simplifying the logic enough to drop the LUT count by quite a bit (which helps with Fmax) (edited)jshamlet
Mar 10, 2020Modified the RSP instruction to work in both directions (SP->R1:R0 or R1:R0->SP) based on any of the four unused CPU status flags. Also modified the LDX instruction to simplify the address logic.jshamlet
Feb 25, 2020Added personal assembler/linker tool chain to the project.jshamlet
Jul 20, 2016Added a 4 and 8-bit character LCD interface with optional backlight and contrast DACs.jshamlet
Jan 7, 2016Added some useful entities developed for various projects, including an epoch timer/alarm clock, clock state detector, and button interface.jshamlet
Nov 16, 2015Added a comment noted that this is a von-neumann style core, where code and data are all placed within the same memory space.jshamlet
Nov 13, 2015Fixed issue with carry flag while executing the CMP and SBC instructions. Previous implementation inverted the carry flag behavior improperly.jshamlet
Sep 23, 2013Removed superfluous reason for BSD licensejshamlet
Sep 18, 2013Updated processor model with several bug fixes.jshamlet
Mar 3, 2012Revised project information to be more current.Hays, Kirk
Dec 22, 2011Modified the WAIT_FOR_INT state to allow the bus to go entirely idle after a WAI instructionjshamlet
Nov 14, 2011Open8 tools synchronized with binutils, Kirk
Sep 22, 2011Checked in new processor model with BRK_Implements_WAI functionality,jshamlet
Sep 21, 2011Discussed current usage of model, including BRK_Implements_WAI option still under testing.jshamlet
Aug 29, 2011Synchronize binutils/ in the svn tree with gnu dev tree of, Kirk
Jul 27, 2011Almost done with timing optimizations. In the process, the model has been flattened to a single entity.jshamlet
Jul 27, 2011Several blocks have been further optimized. Not much in the way of speed, but the model should be about 2% smaller.jshamlet
Jul 27, 2011More bug fixes - interrupts should be 100% functional now.jshamlet
Jun 17, 2011Correct the descriptions for GMSK and SMSK instructions in the Open8 Assembly Language ReferenceHays, Kirk
Jun 15, 2011corrected HTML on project pageHays, Kirk
Jun 15, 2011Fixed a couple of bugs in the CPU core related to address corruptionjshamlet
Jun 14, 2011clr "Clear Accumulator" pseudo-instruction added to binutilsHays, Kirk
Jun 13, 2011binutils updated to 20110613Hays, Kirk
Jun 4, 2011Note that binutils checkin will not be complete until Monday, June 6th.Hays, Kirk
Jun 4, 2011Announcement of binutils source addition to the Open8 repository.Hays, Kirk
Apr 13, 2011Core description updated to clarify that the implementation requires two clock latency for memory and register files.Hays, Kirk
Apr 4, 2011Updated Project Status to reflect current status (Hi-Tech compiler no longer available, assembly manual added, GNU binutils close to release)Hays, Kirk
Mar 10, 2011Added assembly language reference manual for upcoming binutils release.Hays, Kirk
Jan 25, 2011Fixed spelling errorsjshamlet
Jan 24, 2011SVN updated to reflect fixes of 1/18/2011 - revision 10 is now the latest revisionHays, Kirk
Jan 18, 2011Fixed BTT instruction to match actual V8 behaviorjshamlet
Sep 11, 2006Project startedlampret