OpenCores

Documented Verilog UART

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Rx not D-triggered #1
Open dwarf_slogger opened this issue almost 11 years ago
dwarf_slogger commented almost 11 years ago

Input Rx signal goes directly to combinatorial logic (to LUT). It causes time errors in post-synthesis modeling (and FPGA spartan6). Good idea is to use the buffer (clk d-trigger) for Rx.


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