Documented Verilog UART

Jul 30, 2010Add advice on choosing speed.Goddard, Tim
Jun 29, 2010Reduce tested frequency - getting some errors at >57600 baud.Goddard, Tim
Jun 29, 2010Altered the interface to this slightly - the clock rate divider setting has changed to support high baud rates (tested up to 230400 baud). New formula in documentation.Goddard, Tim
Jun 29, 2010Added files to SVN, removing alternate downloadGoddard, Tim
Jun 28, 2010Fixing a bad grammaticalGoddard, Tim
Jun 28, 2010Added license terms to front page to make this as clear as possible.Goddard, Tim
Jun 28, 2010Project setupGoddard, Tim