PCIe_mini (PCI-Express to Wishbone Bridge for Xilinx FPGAs)

When reading data addresses with unaligned access, the core locks up. E.g. word size of 32-bits requires reading addresses multiple of 4 bytes. If odd address is requested, the PCIemini core never responds, host times out, and all further accesses fail.

The core does not support unaligned accesses. I dont remember whether the 8bit was working last time (5 years ago), but if it does work then you have to initiate four separate 8bit accesses for unaligned data. The principle is that the core can only do one wishbone transaction on the simplified bus interface using byte masks, for each pcie request.