Pepelatz MISC
Project maintainers
Details
Name: pepelatz_misc
Created: May 6, 2011
Updated: May 25, 2011
SVN Updated: May 7, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Created: May 6, 2011
Updated: May 25, 2011
SVN Updated: May 7, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Star1you like it: star it!
Other project properties
Category:Processor
Language:Verilog
Development status:Planning
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Planning
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Building team. If any beginner became inetersted in it, email me.
About
Pepelatz MISC is a very small 16-bite processor written on Verilog.
It can be used for learning Verilog HDL and computer low-level architecture.
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.