Programmable DCT Accelarator with 16 bit Microcontroller

Description

The project pairs a DCT Accelarator with a 16 bit Microcontroller. The work was undertaken as a class project for ECE 4273 taught by Dr. Vijay K. Madisetti at the Georgia Institute of Technology, Atlanta GA during the Spring 2007 semester. The project team included Arish Alreja, Chung Ching Lin, Dhruv Srivastava, Girish Jain, Michael Smith, Navraj Singh, Ramanathan Palaniappan, Sunpyo Hong.

This project implements a DCT Hardware accelerator + 16 bit Microcontroller System augmented with an external memory. The system may be used in an application which requires fast computation of DCT’s along with other general purpose computing functions.

The 16 bit Microcontroller used in this system has been written by Dr. Juergen Sauermann. The 64 point DCT core used has been written by Mr. Michael Krepa. The additional memory added to the system uses a memory model developed by Mr. Jamil Khatib. All of the above have been obtained from www.opencores.org .

During the course of the project, the following developments were undertaken

1. Wishbone compliance of the MDCT core (Wishbone Wrapper)
2. Integration of 16 bit MCU, WB compliant MDCT core, and memory to provide a wishbone interconnected system.
3. 16 bit MCU assembly code to execute DCT’s and create 4x4 and 2x2 tiles, this code has also been integrated into the RTOS of the 16 bit MCU.

This design has been simulated and verified on Xilinx Modelsim, but has not yet been tested on a real FPGA.