Marina Garduño, Miguel Angel

QUARK RISK

## Description

8bit RISC microprocessor designed with features like wishbone interconnect to provide it as a tool for System-on-Chip or core (ASIC, CISC processor, etc) development decreasing the cost and effort when a bug is present on the design. This processor _**may**_ be used as core (ASIC, SoC, CISC processor, etc) internal controller(s), so when a bug is present, engineering group **shall** modify only microcode and reprogram it instead of redesign the HDL modules.  
  
**Mechanization Drawing**  
  
![Quark_Mechanization_Drw](/usercontent/img/1456358000)

## License Info.

This project is under license LGPL 3.0  
  
[LGPL 3.0](http://www.gnu.org/licenses/lgpl-3.0.html)

## References

[Microcode (Wikipedia)](https://en.wikipedia.org/wiki/Microcode)


<h2 id="description">Description</h2>
<p>8bit RISC microprocessor designed with features like wishbone interconnect to provide it as a tool for System-on-Chip or core (ASIC, CISC processor, etc) development decreasing the cost and effort when a bug is present on the design. This processor <i><b>may</b></i> be used as core (ASIC, SoC, CISC processor, etc) internal controller(s), so when a bug is present, engineering group <b>shall</b> modify only microcode and reprogram it instead of redesign the HDL modules.
<br /><br />
<b>Mechanization Drawing</b>
<br /><br />
<img src="/usercontent/img/1456358000" alt="Quark_Mechanization_Drw" width="720" height="550" /></p>
<h2 id="license-info">License Info.</h2>
<p>This project is under license LGPL 3.0
<br /><br />
<a href="http://www.gnu.org/licenses/lgpl-3.0.html">LGPL 3.0</a></p>
<h2 id="references">References</h2>
<p><a href="https://en.wikipedia.org/wiki/Microcode">Microcode (Wikipedia)</a></p>


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