RISC Microcontroller
Frequently Ask Questions
What synthesis tool do you use for this
design?
I use Synopsis FPGA Express 3.4.
Have you try the code with other synthesis
tool?
No.
I can't synthesis your code with MAX+plus
II!
MAX+plus II built-in synthesis tool is unable to understand bi-directional
bus. You need to use FPGA Express to synthesis the code and generate the EDF
file. MAX+plus II wil be able to compile the EDF file without any problem.
What other tools do you use?
Altera MAX+plus II 10.0 as the compiler, simulator and programmer. I use Atmel AVR Assembler 1.30 to write and assemble the program of the
microcontroller. Atmel AVR Studio 3.0 is used to simulate the program written in AVR
assembler. HEX2MIF is a small utility to convert HEX file generated by
the assembler to MIF file (the MAX+plus II memory contents format).
What is the targeted device?
Altera FLEX10K20RC240-4, as my lab only provides me with it. It is on the Altera UP1
(University Program) Educational board. If I am not wrong, it is made in
1997. The same VHDL source code can be used for all Altera FLEX, APEX and ACEX
devices. Altera MAX devices are not supported.
Why the VHDL source code is only compatible
with Altera FLEX and APEX devices?
There are 3 device-specific modules used in the design. They are LPM_ADD_SUB
(as adder-subtracter), LPM_ROM (as Program Memory) and LPM_RAM_DQ (as Dual Port
Data Memory).
Can I use the code with Xilinx (or others
company) devices?
No. Refer to the above question. However, you can make the code compatible if
the device-specific modules are replaced with the appropriate modules.
Exactly how fast is your design?
The exact answer is unknown. FPGA Express estimated result for EPF10K20RC240-4
is 12MHz. I have never tested that speed on the evaluation board. For board
testing, I have only tried 6.29MHz. This number came from the on board 25.175MHz
oscillator divided by 4. I have included a frequency divider to divide the clock
by 4 before feeding the whole system so that my design can be run on the
evaluation board. With the FPGA Express settings set to 'device = auto', 'speed
grade = fastest', 'optimized for = speed' and 'preserve hierarchy = on', the
speed results for each Altera device family are as follow:
| Family | Estimated Speed (MHz) |
| ACEX1K | 15 |
| APEX20K | 33 |
| APEK20KE | 33 |
| FLEX10K | 15 |
| FLEX10KA | 15 |
| FLEX10KB | 15 |
| FLEX10KE | 15 |
| FLEX6000 | 21 |
| FLEX8000 | 12 |
* I need to stress that I have
ONLY tested the design
with EPF10K20RC240-4 at 6.29MHz clock speed.
What is the critical path of your design?
More than half of my time and energy are used to optimized the design for
area and speed. I have came to a stage where all the path speed are even,
which I think one must optimize 10 different paths in order to increase 1 MHz
of speed. But that's the limitation of my brain, you can
always make it better if you believe you can. :) If there are no area limitation (if
you got a larger device with more logic cells), there
should be more ways to optimize the design.
I saw c (databus) is driven to "ZZZZZZZZ",
isn't it illegal in an FPGA?
The FLEX10K and most of the FPGAs do not contain tri-state buffers to
implement the Hi-Impedance State (Hi-Z). I have no idea about this until late in my
design progress. I do not know technically how FLEX10K implement the Hi-Z but
the FPGA Express help section mention that it is implemented with
multiplexers. My lecturer told me that it is unwise to use tri-state buffers in FPGA as it will swallow a lot of area (Logic Cells). But anywhere, I have tested
the design successfully on the evaluation board (implementing a simple calculator and
a simple memory game).
I want to start using your design as AT90S1200, what are the rules?
| 1. Study the AT90S1200 datasheet and understand its features and instruction set. |
| 2. DO NOT use the C compiler to write the program. Write them in assembly language using AVR Assembler. |
| 3. There are only 16 registers instead of 32. Use only R16 to R31. NEVER use R0 to R15. |
| 4. Use this include file in the assembler. |
| 5. Keep in mind that there are NO SUCH FEATURES : watchdog timer/reset, analog comparator, EEPROM, I/O ports internal pull-up resistors. |
| 6. DO NOT use the LD and ST instruction to access the general purpose registers, they are not mapped into the data memory space. (Just assume that they do not exist, they are used to access the SRAM) |
| 7. There are NO real power idle and power down modes. However the SLEEP instruction do exist. It does not put the MCU to power saving mode but do wait for an interrupt to occur. When an interrupt occurred, the interrupt service routine is executed and the MCU continue to execute the next instruction immediately after the SLEEP instruction. |
| 8. You MUST simulate the programs you have written with AVR Studio to make sure they are bugs-free. |
What are the rules to use the data
RAM (SRAM) that you have included?
| 1. The SRAM is not a feature of AT90S1200. It is from AT90S2313. Study the SRAM topic in AT90S2313 datasheet. |
| 2. Six load and store instructions can be used along with the Z-Pointer (ZP) to access the data RAM. They are LD/ST indirect with ZP, LD/ST indirect with pre-decrement with ZP and LD/ST indirect with post-increment with ZP. |
| 3. There are NO X-Pointer and Y-pointer. Only Z-Pointer exist. DO NOT use the LD/ST instructions with X-Pointer or Y-Pointer to address the data RAM. |
| 4. DO NOT use the load and store instructions to address the general purpose register and the I/O registers because they are not mapped into the data space. Address only the 128 bytes of data RAM from $60 to $DF. |
| 5. Z-Pointer (ZP) is actually R30. Do not use R30 for other purpose if you intend to use it as the ZP. |
| 6. The stack is still hardware stack (as in AT90S1200) although AT90S2313 uses the SRAM as stack. There are NO stack pointer. There are NO PUSH and PULL instruction. |
| 7. I admit that the SRAM I included is quite useless due to the lack of indirect pointers, the absent of direct addressing and it can not be used as stack. But please kindly forgive me as I am only provided with a very small device, the Altera EPF10K20. My ALL TIME biggest challenge is to fit my design in it while including as much features and instructions as I can (and also increasing its speed). |
How do I use PORT C?
AT90S1200 only has PORT B and PORT D. PORT C is a feature in AT90S2313. Use it
the same way as using PORT B or PORT D. It functions exactly the same. The I/O
addresses for PORT C are PORTC = $15, DDRC = $14 and PINC = $13. Use this
include file so that you can address PORT C easily with
symbolic names rather then hex addresses.
I don't have enough I/O ports, how can I
include PORT A?
PORT A is not included in the design due to my DEVICE SIZE LIMITATION. It can be
added easily by placing another v_port module to v_riscmcu (top level
module) and add PORT D I/O addresses to the v_iodecoder (I/O address
decoder).
Do you still work on this project?
No, I have spent enough time on it. I have documented everything about my
project in my thesis and make it available to everyone through opencores.