Generic AXI interconnect fabric

When I used Robust verilog parser I am getting following error

VERFIY compare failed.

File def_ic_static.txt: line 30: VERIFY(64 in 32, 64)

File def_ic_static.txt: line 31: VERIFY(2 in 2, 3)

File def_ic_static.txt: line 33: VERIFY(3 in 1..8)

File def_ic_static.txt: line 34: VERIFY(6 in 1..16)

Please help.I dint find Robust verilog Parser 1.5 also.

How to solve this?

Hi, were u able to resolve the above mentioned error

Regards, Santhosh