OpenCores

Generic AXI interconnect fabric

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RobustVerilog General error 118 #3
Open ramanathj opened this issue about 8 years ago
ramanathj commented about 8 years ago

When I used Robust verilog parser I am getting following error

VERFIY compare failed.

File def_ic_static.txt: line 30: VERIFY(64 in 32, 64)

File def_ic_static.txt: line 31: VERIFY(2 in 2, 3)

File def_ic_static.txt: line 33: VERIFY(3 in 1..8)

File def_ic_static.txt: line 34: VERIFY(6 in 1..16)

Please help.I dint find Robust verilog Parser 1.5 also.

How to solve this?

santhuvlsi commented over 7 years ago

Hi, were u able to resolve the above mentioned error

Regards, Santhosh


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