OpenCores

Generic AXI interconnect fabric

Project maintainers

Details

Name: robust_axi_fabric
Created: Mar 23, 2011
Updated: Jun 12, 2015
SVN Updated: Jul 3, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 3 reported / 2 solved
Star2you like it: star it!

Other project properties

Category:System on Chip
Language:Verilog
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

Generic AXI interconnect fabric. It is a multi-master, multi-slave non-blocking AXI fabric with round-robin arbitration. Builds Verilog AXI interconnects according to input parameters: master number, slave number, AXI IDs, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.comedatools

Generic AXI master stub
http://opencores.orgproject,axi_master

Generic AXI slave stub
http://opencores.orgproject,axi_slave