RS232 system controller
This page contains files uploaded to the old opencores website as well as images and documents intended for use on other pages in this project. If you want to download this project or browse its svn, you can do so at the overview-page.
| Date | File | Description |
| 2002-09-17 20:43 | b13_safe_09_17_02.zip | This is the complete code base used to test the auto-BAUD-rate version of rs232_syscon. It includes clock multiplier DLLs and Xilinx BRAMs (specific to Xilinx). It has a variable clock generator, used to test out "risc16f84" at various clock speeds from 1-49MHz. |
| 2002-09-17 20:40 | rs232_syscon_autobaud.zip | This is the new auto-BAUD-rate version of rs232_syscon. The zipfile contains the three files necessary to bring it up and get it working on your board. |
| 2002-05-09 00:40 | b11_risc16f84_05_03_02.zip | An example of rs232_syscon being used to debug a small risc16f84 microcontroller. |
| 2002-05-09 00:39 | srec_to_rs232.pl | Perl script used to convert S-record files into rs232_syscon write commands. Used to load code into hardware, one byte at a time. |
| 2001-12-19 22:19 | b10_safe_12_18_01_dual_path.zip | This file contains the latest rs232_syscon core connected to some "byte enable" memory, with the "memory_sizer_dual_path" module connected to the memory. |
| 2001-12-19 22:17 | rs232_syscon_1_00_source.zip | This file contains only "rs232_syscon.v" and "serial.v". The serial port function is in "serial.v" This is the minimum code for using the rs232_syscon module. |
| 2001-12-19 22:15 | rs232_syscon_soc3.zip | This file contains rs232_syscon, connected to some instantiations of Xilinx dual-ported block-RAM. Using the registers, the user can write to the 16-bit side of the memory block, and read from the 32-bit side! The memory block is arranged to be "little endian." |
| 2001-12-19 22:14 | rs232_syscon_soc2.zip | This file contains an additional register block (uses "reg_4_pack.v") and it also shows how the output from the registers is connected to an lcd flat-panel test module, which has a "bouncing pong-ball" on the screen, with grid lines, and an aimable "crosshairs" sight. The lcd flat-panel which was tested was from an IBM 700C laptop computer, and it required a pixel clock of around 25 MHz (this design used 49.152 MHz divided by two.) |
| 2001-12-19 22:14 | rs232_syscon_soc1.zip | This file contains the rs232_syscon connected to a set of 8 registers, 1 of which is read only (uses "reg_8_pack.v" for the registers). It is a good example of how the tri-state data bus connects to the registers. It also has an lcd-panel test block connected to the outputs of the registers, but you can easily delete that part. |
| 2001-12-19 22:12 | rs232_syscon_1_01_xsoc.zip | This file contains the updated rs232_syscon, which supports muxing of the stb_o and we_o lines (in addition to the adr_o lines, which were already muxed between rs232_syscon and the normal bus master.) This file shows how the rs232_syscon can be connected to a host microcontroller. In this case the microcontroller is a 16-bit RISC design, modified from the original XSOC project. This entire design takes up only about 900 Xilinx Virtex slices. The rs232_syscon uses more than half of this logic.... The RISC microcontroller runs at about 32 MHz on the XC2S200 SpartanII chip, without any floorplanning and without any aggressive timing constraints. |
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