Scratch DDR SDRAM Controller

Thank you for sharing the complete project, this is great material and gives me some more to go on why is does not work with my card yet!

The project does not work for me, there are no LED's lighting up just now, but I'm working on it. The only difference I found and changed from your TAR-file is:

NET "dram_addr<4>" LOC = "E4" |IOSTANDARD = SSTL2_I; #F4

The bit 4 address line is located at F4 for 500E and E4 for 1600E. I will look into details if there are something more, but looks OK for now.

But both "Behavior Simulation" and "Post-Route Simulation" gives timing errors.

-snip- Finished circuit initialization process. at 2269 ps(3), Instance /scratch_isim_tb/uut/SDRAM_READER_reg1_6/ : Warning: /X_FF SETUP Low VIOLATION ON CE WITH RESPECT TO CLK; Expected := 0.651 ns; Observed := 0.169 ns; At : 2.269 ns

WARNING: at 24330100 ps: Timing violation in /scratch_isim_tb/DRAM_CHIP/ $setuphold<hold>( Clk:24330100 ps, Addr:24330100 ps,750 ps,750 ps) -snip-

Is this important or can it just be overlooked, I'm not sure.. Isn't the meaning of the scratch_isim_tb.vhd to actually present the correct answer on the dram_dq just as the real FPGA-implementation would?

Post route sim is as close as you can get, and even it isn't perfect. Since I got it working on my board, I haven't looked at the simulator output at all, so those may be out of date. Hardware is the definitive of all three.

Unfortunately, if I can't reproduce the problem, there's not much I can do to fix it, and on my board (the 500k gate Starter Board) the hardware synthesized version works. As that's the only board I got, that's the only one I can fix things for.

The fact that the pinouts are different makes me very cautious about what else might be different with the two boards. Is the SDRAM chip the same?

I'll leave the bug open, but unless I get a 1600k version of the board, there's not much I can do about it.

Thank you for posting ideas! I'm actually right on top of this problem! One more time (I've sesen it before) there are problems with documentation and the actual pin-out of the 1600E-board! And I also messed up (or didn't change) the LED pin-out which also differs. The LED's now light up and as far as I can see the single read/write cycle works!! GREAT!

I still think that this great little useful core shall have folders of synths of different cards with your simple demo-app working out-of-the-box! For example, look at the Zet project for ideas. But of course I'm not sure how you want the project to proceed. I'll be more than willing to commit a reworked 11.2 project file that uses your structure.

This issue can be closed!

The next steps for me is to incorporate this nice core into my FPGA64-sub-project for "full" 64Kbyte RAM and also try and work out into my current baby, a 32-bit retro platform that will release as open-source some day when it feels complete!

I'm not terribly familiar with Subversion, and am not quite sure how to create subfolders. Perhaps you can drop me an email and I'll be happy to create it.

More than happy to accept submissions and patches :)