Scratch DDR SDRAM Controller
Project maintainers
Details
Name: sdram_controller
Created: Sep 11, 2009
Updated: Sep 16, 2012
SVN Updated: Oct 11, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 8 reported / 3 solved
Created: Sep 11, 2009
Updated: Sep 16, 2012
SVN Updated: Oct 11, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 8 reported / 3 solved
Star2you like it: star it!
Other project properties
Category:Memory core
Language:VHDL
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:VHDL
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
DDR SDRAM controller core targeted at the mt46v32m16 chip on the Spartan3e Starter Board. The testbench synthesizes and runs on the targeted hardware. Additionally I've integrated this controller core into an SoC design consisting of a T80 soft cpu with a VGA controller, Flash controller and UART.
The design is more or less frozen, unless I change out soft CPUs and need to integrate again. Further changes will be driven by bug discoveries/reports.
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