Here is an patch to clean up a little bit with librarys:

Index: sdram_support.vhd

--- sdram_support.vhd (revision 24) +++ sdram_support.vhd (working copy) @@ -22,13 +22,7 @@

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL;

----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all;

entity cmd_bank_addr_switch is port( @@ -57,13 +51,8 @@

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.numeric_std.ALL;

----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all;

entity wait_counter is generic( @@ -79,7 +68,7 @@

architecture impl of wait_counter is

• signal reg : std_logic_vector(BITS-1 downto 0);

• signal reg : unsigned(BITS-1 downto 0) := (others => '0');

  begin

@@ -87,7 +76,7 @@ begin if (rst = '1') then done <= '0';

• 	reg <= CONV_STD_LOGIC_VECTOR(CLKS, BITS);

• 	reg <= to_unsigned(CLKS, BITS);

  elsif (rising_edge(clk)) then if (reg > x"00") then done <= '0'; @@ -103,13 +92,11 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL;

----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. library UNISIM; -use UNISIM.VComponents.all; +use UNISIM.VComponents.dcm_sp; +use UNISIM.VComponents.bufg; +use UNISIM.VComponents.oddr2;

entity sdram_dcm is port( @@ -235,13 +222,9 @@

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL;

----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. library UNISIM; -use UNISIM.VComponents.all; +use UNISIM.VComponents.oddr2;

-- just a 2 bit wide ODDR2 entity oddr2_2 is @@ -295,13 +278,9 @@

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL;

----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. library UNISIM; -use UNISIM.VComponents.all; +use UNISIM.VComponents.oddr2;

-- just a 3 bit wide ODDR2 entity oddr2_3 is @@ -371,13 +350,7 @@

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL;

----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all;

-- 2 oddr2_2's entity oddr2_4 is @@ -434,13 +407,9 @@

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL;

----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. library UNISIM; -use UNISIM.VComponents.all; +use UNISIM.VComponents.oddr2;

-- one ODDR2 and 3 4-bit oddr2_4's entity oddr2_13 is @@ -527,13 +496,7 @@

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL;

----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all;

-- 4 4-bit oddr2_4's entity oddr2_16 is @@ -614,13 +577,7 @@

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL;

----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all;

entity inout_switch_2 is port ( @@ -638,13 +595,7 @@

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL;

----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all;

entity inout_switch_16 is port (

Index: sdram_writer.vhd

--- sdram_writer.vhd (revision 24) +++ sdram_writer.vhd (working copy) @@ -22,14 +22,7 @@

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL;

----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM;

---use UNISIM.VComponents.all;

-- Uses ODDR2 registers to generate the required DDR signals. Don't have to be as -- careful with the timings as with sdram_reader, but you need to be able to feed -- the ODDR2's within their setup and hold windows. Or very very hilarious things

Index: sdram.vhd

--- sdram.vhd (revision 24) +++ sdram.vhd (working copy) @@ -22,8 +22,6 @@

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.

Index: scratch.vhd

--- scratch.vhd (revision 24) +++ scratch.vhd (working copy) @@ -22,10 +22,9 @@

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; -use UNISIM.VComponents.all; +use UNISIM.VComponents.bufg; +use UNISIM.VComponents.dcm_sp;

entity scratch is

Index: sdram_reader.vhd

--- sdram_reader.vhd (revision 24) +++ sdram_reader.vhd (working copy) @@ -21,14 +21,7 @@

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL;

----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM;

---use UNISIM.VComponents.all;

-- I strongly suggest you run this in the post-PAR simulator first and then start -- making changes to it after looking at what goes on at the post-PAR level. Don't -- say I didn't warn you. @@ -80,4 +73,4 @@ end if; end process;

-end impl; \ No newline at end of file +end impl;

Index: sdram_init.vhd

--- sdram_init.vhd (revision 24) +++ sdram_init.vhd (working copy) @@ -22,14 +22,7 @@

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL;

----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM;

---use UNISIM.VComponents.all;

entity sdram_init is port( clk_000 : in std_logic;

Index: scratch_isim_tb.vhd

--- scratch_isim_tb.vhd (revision 24) +++ scratch_isim_tb.vhd (working copy) @@ -29,11 +29,8 @@

LIBRARY ieee; USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL;

-library UNISIM; -use UNISIM.VComponents.all;

ENTITY scratch_isim_tb IS port( @@ -145,27 +143,7 @@ );

• -- Clock process definitions
• clk_process :process
• begin

• clk <= '0';

• wait for clk_period/2;

• clk <= '1';

• wait for clk_period/2;

• end process;

• clk <= not clk after clk_period/2;

• rst <= '1', '0' after 5 * clk_period;

• -- Stimulus process
• stim_proc: process
• begin

•  -- hold reset state for 100ms.

•  wait for 100ms;	

•  wait for clk_period*10;

•  -- insert stimulus here 

•  wait;

• end process;
• END;