Kuzmenok, Aleksey

sdram_ctrl

## Short description

This SDRAM controller is optimised for speed. It works efficiently at frequencies higher than 100 Mhz. It's been tested on Altera devices and appears to be completely SOPC Builder Avalon compatible.

## Features

\- Optimised for speed;  
\- Altera Avalon compatible;  
\- Init pause and refresh period can be changed inside the source file;  
\- all others times are fixed to cycles (see src comments);  
\- Configurable bank, row, column widths and clk frequency.

## Status

\- tested  
\- used in real hardware designes


<h2 id="short-description">Short description</h2>
<p>This SDRAM controller is optimised for speed. It works efficiently at frequencies higher than 100 Mhz.  It's been tested on Altera devices and appears to be completely SOPC Builder Avalon compatible.</p>
<h2 id="features">Features</h2>
<p>- Optimised for speed;<br />
- Altera Avalon compatible;<br />
- Init pause and refresh period can be changed inside the source file;<br />
   - all others times are fixed to cycles (see src comments);<br />
- Configurable bank, row, column widths and clk frequency.</p>
<h2 id="status">Status</h2>
<p>- tested<br />
- used in real hardware designes</p>


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sdram_ctrl

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