OpenCores
News
Mar 7, 2019Updated front pageDoin, Jonny
Dec 30, 2016Update verification status. Doin, Jonny
Oct 15, 2016Updated SVN and project home page.Doin, Jonny
Oct 8, 2016Can't update the project SVN due to errors in the OpenCores database. Please send me an email if you want the most recent version.Doin, Jonny
Oct 2, 2016Control logic RTL optimizations, testbench cases update, logic description optimization.Doin, Jonny
Aug 21, 2016Datapath logic descriptionDoin, Jonny
Aug 17, 2016Update on the description html.Doin, Jonny
Aug 1, 2016Update on the description html.Doin, Jonny
Jul 24, 2016Description and logic.Doin, Jonny
Jul 24, 2016Updating logic descriptionDoin, Jonny
Jul 23, 2016Project description and html pagesDoin, Jonny
Jul 22, 2016Updating documentation.Doin, Jonny
Jul 21, 2016Updated VHDL (register init values, minor style issues), and HTML documentation.Doin, Jonny
Jul 21, 2016Update documentationDoin, Jonny
Jul 20, 2016Update logic diagrams and documentation.Doin, Jonny
Jul 20, 2016Changed License to LGPL. Changed testbench for faster data input. Reduced SVN size (deleted intermediate files).Doin, Jonny
Jul 20, 2016Update the testbench cases. Minor logic fixes. Documentation.Doin, Jonny
Jul 19, 2016Updating the front page. Doin, Jonny
Jul 19, 2016Added Development Status. Updated SVN project. Doin, Jonny
Jul 19, 2016Uploaded paper-and-pencil block diagrams of the GV_SHA256 algorithm implemented in VHDL. Doin, Jonny
Jul 18, 2016The GV_SHA256 core is fully compliant to the NIST verification vectors. Written for ASIC targets, but is technology-independent, synthesizable to any FPGA process. Doin, Jonny
Jul 18, 2016HDL files and ISE14 project uploaded. All circuits are verified and working.Doin, Jonny
Jul 15, 2016Project description and initial structure.Doin, Jonny