Mar 7, 2019 | Updated front page | Doin, Jonny |
Dec 30, 2016 | Update verification status. | Doin, Jonny |
Oct 15, 2016 | Updated SVN and project home page. | Doin, Jonny |
Oct 8, 2016 | Can't update the project SVN due to errors in the OpenCores database. Please send me an email if you want the most recent version. | Doin, Jonny |
Oct 2, 2016 | Control logic RTL optimizations, testbench cases update, logic description optimization. | Doin, Jonny |
Aug 21, 2016 | Datapath logic description | Doin, Jonny |
Aug 17, 2016 | Update on the description html. | Doin, Jonny |
Aug 1, 2016 | Update on the description html. | Doin, Jonny |
Jul 24, 2016 | Description and logic. | Doin, Jonny |
Jul 24, 2016 | Updating logic description | Doin, Jonny |
Jul 23, 2016 | Project description and html pages | Doin, Jonny |
Jul 22, 2016 | Updating documentation. | Doin, Jonny |
Jul 21, 2016 | Updated VHDL (register init values, minor style issues), and HTML documentation. | Doin, Jonny |
Jul 21, 2016 | Update documentation | Doin, Jonny |
Jul 20, 2016 | Update logic diagrams and documentation. | Doin, Jonny |
Jul 20, 2016 | Changed License to LGPL. Changed testbench for faster data input. Reduced SVN size (deleted intermediate files). | Doin, Jonny |
Jul 20, 2016 | Update the testbench cases. Minor logic fixes. Documentation. | Doin, Jonny |
Jul 19, 2016 | Updating the front page. | Doin, Jonny |
Jul 19, 2016 | Added Development Status. Updated SVN project. | Doin, Jonny |
Jul 19, 2016 | Uploaded paper-and-pencil block diagrams of the GV_SHA256 algorithm implemented in VHDL. | Doin, Jonny |
Jul 18, 2016 | The GV_SHA256 core is fully compliant to the NIST verification vectors. Written for ASIC targets, but is technology-independent, synthesizable to any FPGA process. | Doin, Jonny |
Jul 18, 2016 | HDL files and ISE14 project uploaded. All circuits are verified and working. | Doin, Jonny |
Jul 15, 2016 | Project description and initial structure. | Doin, Jonny |