Simple UART for FPGA

When I want to send data, the first byte after the u_valid_in sets high was doubled. For exp. my data: {0x7F, 0x55, 0xC1, ...}, I get from the receiver {0x7F, 0x7F, 0x55, 0xC1, ...}.

I solved the issue. It is because if you are sending the next data when rising edge of din_vld. When I change it to send the new data when falling edge of din_vld, the problem resolved