OpenCores

Simple UART for FPGA :: Overview



Project maintainers

Details

Name: simple_uart_for_fpga
Created: Jun 1, 2016
Updated: Mar 28, 2019
SVN Updated: Jun 2, 2016
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Star1you like it: star it!

Other project properties

Category:Communication controller
Language:VHDL
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: Others

Description

Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.

© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.