SoM-ARM9-CycloneIVGX
May 29 2012
On the PCI bus the clock signals should be length equalized. In Altium designer this is done with an interactive length tuning
function.
We have three clock signals
1. Micrel SoC PCI clock
2. FPGA PCI clock
3. USB PCI clock
The USB PCI clock has the largest distance. When routed this signal has a total length of 29.5 mm.
On the other two signals we use the interactive length tuning functions. After tuning the length of the two other clock signals
are 29.868 respectively 29.278. That is fine.
Same thing applies to SDRAM clock. Clock line from Micrel SoC to memory is 95.16 mm. After length tuning the feedback signal is
95.75 mm
May 25 2012
Interactive pin/part swapping. That was the key to success with routing of PCI signals between SoC and FPGA.
The autorouter did not manage to route this signals. But with the use of the interactive pin swapping in Altium designer
it was possible to manually route all these signals. In only one signal plane !
May 23 2012
Turns Altium designer has very good support pin swapping. This useful not only for 74 family devices but for FPGAs.
On the FPGA symbol you can define any number of IO groups. Each pin in an IO group can be swapped with any other
in that group. You can do this per IO bank or in any other way convenient for your design.
For this design the following groups are defined:
1. FLASH
2. FPGAIO5
3. FPGAIO6
4. GPIO
5. PCI
For FPGA IO there are two groups with different VCCIO. These are connected to IO bank 5 respectively 6.
When this is done you can issue Tools/PinPart Swapping/Automatic net pin Optimizer
This will create the shortest possible trace lengths.
May 21 2012
All components placed on board.
Major routing effort needed within these areas
1. PCI between Micrel CPU, USB and FPGA. CLK signals also should be length matched
2. FPGAIO towards SO-DIMM connector.
3. memory bus. Should not be too complicated. Memories are placed on upper side of PCB with CPU down right.
1 and 2 should be simplified with pin swapping enabled on FPGA. How do we do that ?
May 14 2012
All symbols in place and schematic 99% finished!
On the To-Do list are connections for GPIO from CPU, some interrupt sources (like the DC/DC controller).
Schematic is drawn hierarchical. Altium designer support both flat and hierarchical. I think hierarchical is
more useful when handled on a computer and flat is better if you have a printed copy.
Altium have a function called harness. A harness is a bunch of signal that you combine into one object. Normally related
signals like an expansion bus. The bus could be made up of data, address and control signals. All these signals
can be combined into one object with the use of a harness. That makes the design more readable. Especially on the top level
schematic where you do not need so many signals.
Schematic is added to the project.
May 8 2012
Fortunately a lot of the symbols are available from Altium.
The following components have schematic symbols and PCB footprints:
ALTERA Cyclone IV GX, EP4CGX22CF19I7
FTDI FT230X
Micron MT4M16, SDRAM
Some needs to be defined. Most notable are:
Micrel KSZ8095P
NEC uDP720101
TPS65217A
For many types of packages there is wizard to create PCB footprints. This saves a lot of time. We will use that
for all BGA packages.
Schematic will be written hierarchical. That should make reuse of schematic easier for other projects.
May 7 2012
For this project I will be using a design tool which is new to me. Altium designer. There are a bunch of functions that I consider vital to be able to succeed with this project namely
1. Support for high speed differential signals. Length matching and impedance setting
2. Length matching of signals (in this case clock signals on the PCI bus)
3. Signal integrity simulation support based on IBIS models
Altium Designer includes these functions. Altium designer also have the following
1. Extensive libraries including schematic symbols and PCB footprints for Altera FPGAs, FTDI USB chips, SDRAM and FLASH memories
2. An auto router
Altium designer also have some other interesting functions. One that could prove useful later on when we use the FPGA as a coprocessor is the C to hardware tool.
Now lets start up the schematic designer