van Rantwijk, Joris

SpaceWire Light

Love your work but....
Only the ErrorRest->ErrorWait transition time should be 6.4us.
Transition from ErrorWait  to Ready should happen after 12.8us.
Timeouts from Ready, Started and Connected should also happen after 12.8us.

Incorrect timeouts

Hi,

I'm currently trying to communicate with this IP in an A3P1000L from the autostart side and with a famous spacewire brick on the linkstart side.

I am able to communicate but to do that I must perform many resets (number is random) until the IP and the brick manage to connect.
Seems like the out of reset state is not always the same.

Has anyone encounter this situation?

Clément

OUT OF RESET PB

In Page 9, after Fig. 6 it should say: "A received time-code is announced by a single-cycle pulse on tick_out." Instead of: "A received time-code is announced by a single-cycle pulse on tick_in."

Correction in manual document

Dear Joris,

First of all, thank you very much for such an useful core and rtems drivers.

We have some problems, you may give idea to solve this problem.
We have Xilinx vc707 board. Since it has 200 mhz system clock, we didn't use DCM to generate 200 mhz clock for spacewire. Morover, we have not used spacewire signals as differential but as ttl. Let me print down our spacewirelight related parts of our leon3mp design, so you can understand more clear.

in constraint file (.xdc):
set_property PACKAGE_PIN F35 [get_ports {  spw_di   }]
set_property IOSTANDARD LVCMOS18 [get_ports { spw_di  }]
set_property PACKAGE_PIN G42 [get_ports {  spw_do   }]
set_property IOSTANDARD LVCMOS18 [get_ports { spw_do  }]
set_property PACKAGE_PIN K40 [get_ports {  spw_si   }]
set_property IOSTANDARD LVCMOS18 [get_ports { spw_si  }]
set_property PACKAGE_PIN G41 [get_ports {  spw_so   }]
set_property IOSTANDARD LVCMOS18 [get_ports { spw_so  }]

in leon3mp.vhd:

...
	spw_clk	  		: in  std_ulogic;
--    spw_rxdp      : in  std_logic_vector(0 to 2);
--    spw_rxdn      : in  std_logic_vector(0 to 2);
--    spw_rxsp      : in  std_logic_vector(0 to 2);
--    spw_rxsn      : in  std_logic_vector(0 to 2);
--    spw_txdp      : out std_logic_vector(0 to 2);
--    spw_txdn      : out std_logic_vector(0 to 2);
--    spw_txsp      : out std_logic_vector(0 to 2);
--    spw_txsn      : out std_logic_vector(0 to 2)
	
	spw_di	  		: in  std_logic;
	spw_si	  		: in  std_logic;
	spw_do         : out std_logic;
    spw_so         : out std_logic

....

signal spw_clkl   : std_ulogic;
signal spw_tick_in: std_logic;
--signal spw_di: std_logic;
--signal spw_si: std_logic;
--signal spw_do: std_logic;
--signal spw_so: std_logic;

....

spw0: spwamba
      generic map (
         tech        => memtech,
         hindex      => 12,--CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
         pindex      => 12,
         paddr       => 12,
         pirq        => 12,
         sysfreq     => real(CPU_FREQ) * 1000.0,
         txclkfreq   => 200.0e6,
         rximpl      => impl_fast,
         rxchunk     => 4,
         tximpl      => impl_fast,
         timecodegen => true,
         rxfifosize  => 8,
         txfifosize  => 8,
         desctablesize => 10,
         maxburst    => 3 )
      port map (
         clk     => clkm,
         rxclk   => lclk,
         txclk   => lclk,
         rstn    => rstn,
         apbi    => apbi,
         apbo    => apbo(12),
         ahbi    => ahbmi,
         ahbo    => ahbmo(12),--CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
         tick_in => spw_tick_in,
         tick_out => open,
         spw_di  => spw_di,
         spw_si  => spw_si,
         spw_do  => spw_do,
         spw_so  => spw_so );

--   spw_rxd_pad: inpad_ds
--      generic map (padtech, lvds, x25v)
--      port map (spw_rxdp(0), spw_rxdn(0), spw_di);
--   spw_rxs_pad: inpad_ds
--      generic map (padtech, lvds, x25v)
--      port map (spw_rxsp(0), spw_rxsn(0), spw_si);
--   spw_txd_pad: outpad_ds
--      generic map (padtech, lvds, x25v)
--      port map (spw_txdp(0), spw_txdn(0), spw_do, '0');
--   spw_txs_pad: outpad_ds
--      generic map (padtech, lvds, x25v)
--      port map (spw_txsp(0), spw_txsn(0), spw_so, '0');


 
	-- Use 2nd GPTIMER unit to generate external tick_in signal.
   spw_tick_in <= gpto.tick(2) when CFG_GPT_ENABLE /= 0 else '0';

...

Then, we have used your spacewirelight drivers and then spwltest.c file as a reference to send and receive spacewire packets. We couldn't receive spacewire packets yet, but we firstly want to see if we can send spacewire packets. We haven't seen them yet. The code doesn't give any error messages. It seems as if it is really sending. Here how we have initialized spacewirelight in rtems side:

rtems_status_code ret;
    int i;
    /* Create TX data pool. */
	for (i = 0; i < MAX_BLOCK_SIZE; i++) {
		int v = ((i & 1) << 7) | ((i & 2) << 5) |
				((i & 4) << 3) | ((i & 8) << 1) |
				((i & 16) >> 1) | ((i & 32) >> 3) |
				((i & 64) >> 5) | ((i & 128) >> 7);
		v += (i >> 8);
		txpool[i] = v;
	}

    spw_index = 0;
    printf("Opening driver for device index %u\n"
           "  options: rxbufs=%u, txbufs=%u, rxbufsize=%u, txbufsize=%u\n",
           spw_index,
           spw_opt.rxbufs, spw_opt.txbufs,
           spw_opt.rxbufsize, spw_opt.txbufsize);

    ret = spwl_open(&spwh, spw_index, &spw_opt);
    if (ret != RTEMS_SUCCESSFUL)
    {
    	printf("ERROR: SpacewireLight Could not Be Opened\n");
        if (ret == RTEMS_INVALID_NUMBER)
            printf("ERROR: SpaceWire Light core not found\n");
    }

    do_set_link_speed(200);

    spw_mode = SPWL_LINKMODE_START;
    ret = spwl_set_linkmode(spwh, spw_mode);
    if (ret != RTEMS_SUCCESSFUL)
    	printf("ERROR: Link mode not set\n");

   printf("SpaceWire Driver Initialized\n");
}


void sendTestData(void)
{
	rtems_status_code ret;
	unsigned int f;
	size_t p;
	p=100;

	f = SPWL_EOP;
	txbuf_desc.data = txpool;
	txbuf_desc.nbytes = 100;
	txbuf_desc.eop = SPWL_EOP;//0;
	ret = spwl_send(spwh, &txbuf_desc, p, &p, f | SPWL_WAIT);
//	ret = spwl_send_txbuf(spwh, &txbuf_desc, SPWL_WAIT);
	if (ret != RTEMS_SUCCESSFUL)
		printf("spwl_send_txbuf error!!!\n");
	else
		printf("Sending Test Data\n");

}

I hope these may help you to see  the problem. I can give additional information.

Thank you very much,

Vakkas

Could not see the signals yet

The idea is to remove the TX clock generation from the core and just source it from the external pin. That will give user more control, for example user may source it directly from PLL rather then using your clock dividing logic. 

Then, both RX and TX buffers should act DDR to achieve maximum speed of 400 Mbaud with FPGA.

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