Drange, Geir

SPDIF Interface

## FPGA Synthesis results

Resource utilization for a minimum version and an all-bells-n-whistles version of the SPDIF cores are shown below for two popular FPGA targets. Exact numbers will depend on tool used, tool settings and target architecture.

## Recevier

**SPDIF Receiver**

**Altera Cyclone**

**Xilinx Spartan 3**

_Minimum_:

DATA\_WIDTH = 16  
ADDR\_WIDTH = 8  

CH\_ST\_CAPTURE = 0

WISHBONE\_FREQ = 33

203MHz

401 LE's

2,048kbit ram

110MHz

246 slices

18,432kbit ram

_All features_:

DATA\_WIDTH = 32

ADDR\_WIDTH = 13

CH\_ST\_CAPTURE = 8

WISHBONE\_FREQ = 33

156MHz

2259 LE's

131,072kbit ram

67MHz

1376 slices

147,456kbit ram

## Transmitter

**SPDIF Transmitter**

**Altera Cyclone**

**Xilinx Spartan 3**

_Minimum_:

DATA\_WIDTH = 16

ADDR\_WIDTH = 8

USER\_DATA\_BUF = 0

CH\_STAT\_BUF = 0

196MHz

239 LE's

2,048kbit ram

82MHz

141 slices

18,432kbit ram

_All features_:

DATA\_WIDTH = 32

ADDR\_WIDTH = 13

USER\_DATA\_BUF = 1

CH\_STAT\_BUF = 1

85MHz

1477 LE's

98,304kbit ram

36MHz

1046 slices

110,592kbit ram


<h2 id="fpga-synthesis-results">FPGA Synthesis results</h2>
<p>Resource utilization for a minimum version and an all-bells-n-whistles version of the SPDIF cores are shown below for two popular FPGA targets. Exact numbers will depend on tool used, tool settings and target architecture.</p>
<h2 id="recevier">Recevier</h2>
<p>
<div><table border="1" cellpadding="2" cellspacing="2">
<tr>
<td>
<div><b>SPDIF Receiver</b></div>

</td>
<td>
<div><b>Altera Cyclone</b></div>

</td>
<td>
<div><b>Xilinx Spartan 3</b></div>

</td>
</tr>
<tr>
<td>
<div><i>Minimum</i>:</div>
DATA_WIDTH = 16<br />
ADDR_WIDTH = 8<br />
<div>CH_ST_CAPTURE = 0</div>
<div>WISHBONE_FREQ = 33</div>

</td>
<td>
<div>203MHz</div>
<div>401 LE's</div>
<div>2,048kbit ram</div>

</td>
<td>
<div>110MHz</div>
<div>246 slices</div>
<div>18,432kbit ram</div>

</td>
</tr>
<tr>
<td>
<div><i>All features</i>:</div>
<div>DATA_WIDTH = 32</div>
<div>ADDR_WIDTH = 13</div>
<div>CH_ST_CAPTURE = 8</div>
<div>WISHBONE_FREQ = 33</div>
<div> </div>

</td>
<td>
<div>156MHz</div>
<div>2259 LE's</div>
<div>131,072kbit ram</div>

</td>
<td>
<div>67MHz</div>
<div>1376 slices</div>
<div>147,456kbit ram</div>

</td>
</tr>
</table>
</div>

</p>
<h2 id="transmitter">Transmitter</h2>
<p>
<div><table border="1" cellpadding="2" cellspacing="2">
<tr>
<td>
<div><b>SPDIF Transmitter</b></div>

</td>
<td>
<div><b>Altera Cyclone</b></div>

</td>
<td>
<div><b>Xilinx Spartan 3</b></div>

</td>
</tr>
<tr>
<td>
<div><i>Minimum</i>:</div>
<div>DATA_WIDTH = 16</div>
<div>ADDR_WIDTH = 8</div>
<div>USER_DATA_BUF = 0</div>
<div>CH_STAT_BUF = 0</div>

</td>
<td>
<div>196MHz</div>
<div>239 LE's</div>
<div>2,048kbit ram</div>

</td>
<td>
<div>82MHz</div>
<div>141 slices</div>
<div>18,432kbit ram</div>

</td>
</tr>
<tr>
<td>
<div><i>All features</i>:</div>
<div>DATA_WIDTH = 32</div>
<div>ADDR_WIDTH = 13</div>
<div>USER_DATA_BUF = 1</div>
<div>CH_STAT_BUF = 1</div>
<div> </div>

</td>
<td>
<div>85MHz</div>
<div>1477 LE's</div>
<div>98,304kbit ram</div>

</td>
<td>
<div>36MHz</div>
<div>1046 slices</div>
<div>110,592kbit ram</div>

</td>
</tr>
</table>
</div>

</p>


SPDIF Receiver	Altera Cyclone	Xilinx Spartan 3
Minimum: DATA_WIDTH = 16 ADDR_WIDTH = 8 CH_ST_CAPTURE = 0 WISHBONE_FREQ = 33	203MHz 401 LE's 2,048kbit ram	110MHz 246 slices 18,432kbit ram
All features: DATA_WIDTH = 32 ADDR_WIDTH = 13 CH_ST_CAPTURE = 8 WISHBONE_FREQ = 33	156MHz 2259 LE's 131,072kbit ram	67MHz 1376 slices 147,456kbit ram

SPDIF Transmitter	Altera Cyclone	Xilinx Spartan 3
Minimum: DATA_WIDTH = 16 ADDR_WIDTH = 8 USER_DATA_BUF = 0 CH_STAT_BUF = 0	196MHz 239 LE's 2,048kbit ram	82MHz 141 slices 18,432kbit ram
All features: DATA_WIDTH = 32 ADDR_WIDTH = 13 USER_DATA_BUF = 1 CH_STAT_BUF = 1	85MHz 1477 LE's 98,304kbit ram	36MHz 1046 slices 110,592kbit ram

Browse

SPDIF Interface

FPGA Synthesis results

Recevier

Transmitter