internal samp_clk appears to stay in phase relative to sck_o regardless of CPHA setting. (CPOL = 0 for the case I tested). Expected behavior (if I'm reading the code comments correctly) is for samp_clk to switch phase relative to sck_o depending on CPHA setting.
It appears that samp_clk has correct idle polarity, but that sck_o starts a cycle (of spi_2x_clk) earlier in cpha=1 than in cpha=0, canceling out the change in polarity of samp_clk from the cpha setting.
I found (and fixed) 2 problems related with this bug, in module spi_master.vhd:
1) The first problem was that the internal base clock generated for spi_sck_o (spi_clk / spi_n_clk) had a poorly designed clock enable that caused loss of phase sync with the internal core_clk / core_n_clk generator when enabled/released. THE FIX: The clock generator was redesigned, with only one pair of FFDs responsible to generate a single differential pair of clocks for the whole spi_master core;
2) The second problem was also in the clock generator, and was related with the inference of a registered output clock for the SPI clock, spi_sck_o, to guarantee strict phase alignment with the internal fsm clock and MOSI data. The problem was that this inferred register, a FDCE (FFD with clock enable) is sensitive to the data hold time of the CE control, and can glitch. THE FIX: spi_sck_o FDCE register was substituted for an output MUX that adds a LUT delay to the SCK line. That extra logic layer degrades upper operating frequency by degrading data setup time of the MISO input, but is much safer to synthesize, and won´t glitch;
These fixes are uploaded with the newest SVN files, that also contain a number of other improvements.
Please Jacob, take a look and see if the bug was corrected. I will not close this bug without confirmation.
This bug has been solved in version v0.97.0083, updated in the SVN. Please confirm.