Please if you are using this core, report if the marked bugs (CPHA='1', bit alignment) are solved for your toolchain.
You can send me e-mail to firstname.lastname@example.org
I have confirmation from people using Xilinx ISE 13.1, 12.4 and 12.1 with WebPack, Altium + ISE 12.3, Synopsys and Altera tools.
I would like to know if the VHDL style used in this core works for your toolchain, and if not, what seems to be the problem.
My goal is to find a description style that is as friendly as possible to synthesis tools.
The scope screens below show a CPOL=1, CPHA=1 spi transaction. Debug signals show the slave internal state and slave flow control signals for the read/write ports. The spi_master and spi_slave cores are verified in FPGA hardware at 100MHz (50MHz spi clock) with 0 ns of SCK-to-MOSI delay and less than 2ns of SCK-to-MISO delay.
In the example, the slave is used with wren_i permanently tied to HIGH. The parallel input data is sampled from di_i at start of transmission, until the first SPI SCK edge. For continuous transfers, the data at di_i is sampled again every falling edge on state 1.
The scope screens below show 2 examples of continuous transfers: for CPOL=1, CPHA=0 and CPOL=0, CPHA=0 spi modes. The words are loaded when 'di_req' line goes to '1'. Data is presented to the port di_i and wren_i is pulsed to write the data word.
In the screen on the right, the 1st 'di_req' data request (requesting data for the second word) is ignored by the slave parallel interface driver, and MISO is cleared (others => '0') for that word. The 3rd word is loaded normally ('wren' is strobed in time for the transfer).