SPI Master/Slave Interface

Hello I am using Altera Quartus 12.1 and SPI_MASTER version: v1.15.0136

When I put the signal rst_i = '1 'or the system is in stand, with no data to transmit clock SCLK keeps coming. Is not maintained at a constant level '1 '. It may be problem synthesizer or always wrong?

settings are: N => 8 CPOL => '1 ', CPHA => '1 ', PREFETCH => 1, SPI_2X_CLK_DIV => 2

sclk_i = pclk_i = 50 Mhz spi clock = 25 Mhz

I can send a trap to the values ??of inputs and outputs. Tested on a FPGA (Cyclone IV)