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SPI Master/Slave Interface :: Bugtracker

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Testbench Out of Date #12
Open elias.koegel opened this issue over 3 years ago— assigned to: jdoinBug
elias.koegel commented over 3 years ago

The testbench is out of date. Some of the points:

  • the ports of modules are outdated
  • not fully parametrized, parameters are not propageted
  • reset sequence works only out of luck, not because a working reset
  • registers in the spi master and slave are not reseted properly
  • no real loopback despide stated
  • no check for bulk and single transfer
  • no free running clocks of slave and master
  • no stop condition for simulation
  • ... The Master and Slave itself looking interesting and far better than most alternatives. Unfortunatly it costed me some time to get the buggy testbench running.

Following you find my readapted testbench. It's not perfect, but functional. I tested it with modelsim (Questa Sim 10.0).

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL;

library work; use work.all;

ENTITY spi_loopback_test IS GENERIC (
N : positive := 8; -- 32bit serial word length is default CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default) CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase. PREFETCH : positive := 3; -- prefetch lookahead cycles SPI_2X_CLK_DIV : positive := 1 -- for a 100MHz sclk_i, yields a 10MHz SCK );
END spi_loopback_test;

ARCHITECTURE behavior OF spi_loopback_test IS

--=========================================================
-- Component declaration for the Unit Under Test (UUT)
--=========================================================

COMPONENT spi_loopback
PORT(
	m_clk_i : IN std_logic;
	m_rst_i : IN std_logic;
	m_spi_miso_i : IN std_logic;
	m_di_i : IN std_logic_vector(N-1 downto 0);
	m_wren_i : IN std_logic;
	s_clk_i : IN std_logic;
	s_spi_ssel_i : IN std_logic;
	s_spi_sck_i : IN std_logic;
	s_spi_mosi_i : IN std_logic;
	s_di_i : IN std_logic_vector(N-1 downto 0);
	s_wren_i : IN std_logic;          
	m_spi_ssel_o : OUT std_logic;
	m_spi_sck_o : OUT std_logic;
	m_spi_mosi_o : OUT std_logic;
	m_di_req_o : OUT std_logic;
	m_do_valid_o : OUT std_logic;
	m_do_o : OUT std_logic_vector(N-1 downto 0);
	m_do_transfer_o : OUT std_logic;
	m_wren_o : OUT std_logic;
	-- m_wren_ack_o : OUT std_logic;
	m_rx_bit_reg_o : OUT std_logic;
	m_state_dbg_o : OUT std_logic_vector(5 downto 0);
	m_core_clk_o : OUT std_logic;
	m_core_n_clk_o : OUT std_logic;
	m_sh_reg_dbg_o : OUT std_logic_vector(N-1 downto 0);
	s_spi_miso_o : OUT std_logic;
	s_di_req_o : OUT std_logic;
	s_do_valid_o : OUT std_logic;
	s_do_o : OUT std_logic_vector(N-1 downto 0);
	s_do_transfer_o : OUT std_logic;
	s_wren_o : OUT std_logic;
	-- s_wren_ack_o : OUT std_logic;
	-- s_rx_bit_reg_o : OUT std_logic;
	s_state_dbg_o : OUT std_logic_vector(5 downto 0)
	);
END COMPONENT;

--=========================================================
-- constants
--=========================================================
constant fifo_memory_size : integer := 16;
shared variable ENDSIM : boolean;

--=========================================================
-- types
--=========================================================
type fifo_memory_type is array (0 to fifo_memory_size-1) of std_logic_vector (31 downto 0);

--=========================================================
-- signals to connect the instances
--=========================================================
-- internal clk and rst
signal m_clk : std_logic := '0';                -- clock domain for the master parallel interface. Must be faster than spi bus sck.
signal s_clk : std_logic := '0';                -- clock domain for the slave parallel interface. Must be faster than spi bus sck.
signal rst : std_logic := 'U';
-- spi bus wires
signal spi_sck : std_logic;
signal spi_ssel : std_logic;
signal spi_miso : std_logic;
signal spi_mosi : std_logic;
-- master parallel interface
signal di_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_m : std_logic_vector (N-1 downto 0) := (others => 'U');
signal do_valid_m : std_logic;
signal do_transfer_m : std_logic;
signal di_req_m : std_logic;
signal wren_m : std_logic := '0';
signal wren_o_m : std_logic := 'U';
-- signal wren_ack_o_m : std_logic := 'U';
signal rx_bit_reg_m : std_logic;
signal state_m : std_logic_vector (5 downto 0);
signal core_clk_o_m : std_logic;
signal core_n_clk_o_m : std_logic;
signal sh_reg_m : std_logic_vector (N-1 downto 0) := (others => '0');
-- slave parallel interface
signal di_s : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_s : std_logic_vector (N-1 downto 0);
signal do_valid_s : std_logic;
signal do_transfer_s : std_logic;
signal di_req_s : std_logic;
signal wren_s : std_logic := '0';
signal wren_o_s : std_logic := 'U';
-- signal wren_ack_o_s : std_logic := 'U';
-- signal rx_bit_reg_s : std_logic;
signal state_s : std_logic_vector (5 downto 0);
-- signal sh_reg_s : std_logic_vector (N-1 downto 0);

--=========================================================
-- Clock period definitions
--=========================================================
constant m_clk_period : time := 11 ns;          -- 100MHz master parallel clock
constant s_clk_period : time :=  9 ns;          -- 100MHz slave parallel clock

BEGIN

--=========================================================
-- Component instantiation for the Unit Under Test (UUT)
--=========================================================

Inst_spi_loopback: entity work.spi_loopback(Structural)
     generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)

-- Inst_spi_loopback: spi_loopback port map( ----------------MASTER----------------------- m_clk_i => m_clk, m_rst_i => rst, m_spi_ssel_o => spi_ssel, m_spi_sck_o => spi_sck, m_spi_mosi_o => spi_mosi, m_spi_miso_i => spi_miso, m_di_req_o => di_req_m, m_di_i => di_m, m_wren_i => wren_m, m_do_valid_o => do_valid_m, m_do_o => do_m, ----- debug ----- m_do_transfer_o => do_transfer_m, m_wren_o => wren_o_m, -- m_wren_ack_o => wren_ack_o_m, m_rx_bit_reg_o => rx_bit_reg_m, -- m_state_dbg_o => state_m, m_core_clk_o => core_clk_o_m, m_core_n_clk_o => core_n_clk_o_m, m_sh_reg_dbg_o => sh_reg_m, ----------------SLAVE----------------------- s_clk_i => s_clk, s_spi_ssel_i => spi_ssel, s_spi_sck_i => spi_sck, s_spi_mosi_i => spi_mosi, s_spi_miso_o => spi_miso, s_di_req_o => di_req_s, s_di_i => di_s, s_wren_i => wren_s, s_do_valid_o => do_valid_s, s_do_o => do_s, ----- debug ----- s_do_transfer_o => do_transfer_s, s_wren_o => wren_o_s -- s_wren_ack_o => wren_ack_o_s -- s_rx_bit_reg_o => rx_bit_reg_s -- s_state_dbg_o => state_s -- s_sh_reg_dbg_o => sh_reg_s );

--=========================================================
-- Clock generator processes
--=========================================================
m_clk_process : process
begin
    if ENDSIM=false then
        m_clk <= '0';
        wait for m_clk_period/2;
        m_clk <= '1';
        wait for m_clk_period/2;
    else
        wait;
    end if;
end process m_clk_process;

s_clk_process : process
begin
    if ENDSIM=false then
        s_clk <= '0';
        wait for s_clk_period/2;
        s_clk <= '1';
        wait for s_clk_period/2;
    else
        wait;
    end if;
end process s_clk_process;

--=========================================================
-- rst_i process
--=========================================================
rst <= '0', '1' after 20 ns, '0' after 100 ns; -- Error: High or Low active Reset?!


--=========================================================
-- Master interface process
--=========================================================
master_tx_fifo_proc: process is
    variable fifo_memory : fifo_memory_type := 
        (X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789",
         X"12345678",X"beefbeef",X"fee1600d",X"f158ba17",X"5ee1a7e3",X"101096da",X"600ddeed",X"deaddead");
    variable fifo_head : integer range 0 to fifo_memory_size-1;
    variable mapping : std_logic_vector (31 downto 0);
begin
    wait until m_clk'event and m_clk = '1';
    di_m <= (others => '0');
    wren_m <= '0';
    fifo_head := 0;
    wait until rst = '1';
    wait until rst = '0';
    wait until m_clk'event and m_clk = '1';             -- 
    wait until m_clk'event and m_clk = '1';             -- 
    -- Error: Master output di_req_o is not sensitive for reset: wait until di_req_m = '1'; -- wait shift register request for data
    for cnt in 0 to (fifo_memory_size/2)-1 loop
        fifo_head := cnt;                               -- pre-compute next pointer 
        wait until m_clk'event and m_clk = '1';         -- 
        mapping := fifo_memory(fifo_head);              -- place data into tx_data input bus
        di_m <= mapping(N-1 downto 0);                  -- place data into tx_data input bus
        wait until m_clk'event and m_clk = '1';         -- 
        wren_m <= '1';                                  -- write data into spi master
        wait until m_clk'event and m_clk = '1';         -- 
        wait until m_clk'event and m_clk = '1';         -- 
        wren_m <= '0';                                  -- remove write enable signal
        wait until di_req_m = '1';                      -- wait shift register request for data
        wait until m_clk'event and m_clk = '1';         -- 
        wait until m_clk'event and m_clk = '1';         -- bigger break to see single byte transmission
        wait until m_clk'event and m_clk = '1';         -- 
        wait until m_clk'event and m_clk = '1';         -- 
        wait until m_clk'event and m_clk = '1';         -- 
        wait until m_clk'event and m_clk = '1';         -- 
        wait until m_clk'event and m_clk = '1';         -- 
        wait until m_clk'event and m_clk = '1';         -- 
    end loop;
    
    -- same error again: wait until spi_ssel = '1';
    wait for 1000 ns;
    for cnt in (fifo_memory_size/2) to fifo_memory_size-1 loop
        fifo_head := cnt;                               -- pre-compute next pointer 
        wait until m_clk'event and m_clk = '1';         -- 
        mapping := fifo_memory(fifo_head);              -- place data into tx_data input bus
        di_m <= mapping(N-1 downto 0);                  -- place data into tx_data input bus
        wait until m_clk'event and m_clk = '1';         -- 
        wren_m <= '1';                                  -- write data into spi master
        wait until m_clk'event and m_clk = '1';         -- 
        wait until m_clk'event and m_clk = '1';         -- 
        wren_m <= '0';                                  -- remove write enable signal
        wait until di_req_m = '1';                      -- wait shift register request for data
    end loop;
    
    wait for 1000 ns;
    ENDSIM := true;
    wait;
end process master_tx_fifo_proc;


--=========================================================
-- Slave interface process
--=========================================================
di_s <= do_s;                                           -- loop data from output to input

slave_tx_fifo_proc: process is
begin
    wren_s <= '0';
    while 1 = 1 loop
        wait until di_req_s = '1';                      -- wait shift register request for data
        wait until s_clk'event and s_clk = '1';         -- 
        wait until s_clk'event and s_clk = '1';         -- 
        wren_s <= '1';                                  -- write data into shift register
        wait until s_clk'event and s_clk = '1';         -- 
        wait until s_clk'event and s_clk = '1';         -- 
        wren_s <= '0';                                  -- remove write enable signal
    end loop;
    wait;
end process slave_tx_fifo_proc;

END ARCHITECTURE behavior;

elias.koegel commented over 3 years ago

Updated Code, because the html-conversion messed up important parts of the description:

<!-- HTML generated using hilite.me --><div style="background: #ffffff; overflow:auto;width:auto;border:solid gray;border-width:.1em .1em .1em .8em;padding:.2em .6em;"><pre style="margin: 0; line-height: 125%"><span style="color: #008800; font-weight: bold">LIBRARY</span> <span style="color: #0e84b5; font-weight: bold">ieee</span>;

<span style="color: #008800; font-weight: bold">USE</span> <span style="color: #0e84b5; font-weight: bold">ieee.std_logic_1164.ALL</span>; <span style="color: #008800; font-weight: bold">USE</span> <span style="color: #0e84b5; font-weight: bold">ieee.numeric_std.ALL</span>;

<span style="color: #008800; font-weight: bold">library</span> <span style="color: #0e84b5; font-weight: bold">work</span>; <span style="color: #008800; font-weight: bold">use</span> <span style="color: #0e84b5; font-weight: bold">work.all</span>;

<span style="color: #008800; font-weight: bold">ENTITY</span> <span style="color: #BB0066; font-weight: bold">spi_loopback_test</span> <span style="color: #008800; font-weight: bold">IS</span> <span style="color: #008800; font-weight: bold">GENERIC</span> (
N <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">positive</span> <span style="color: #333333">:=</span> <span style="color: #0000DD; font-weight: bold">8</span>; <span style="color: #888888">-- 32bit serial word length is default</span> CPOL <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span> <span style="color: #333333">:=</span> <span style="color: #0044DD">'0'</span>; <span style="color: #888888">-- SPI mode selection (mode 0 default)</span> CPHA <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span> <span style="color: #333333">:=</span> <span style="color: #0044DD">'1'</span>; <span style="color: #888888">-- CPOL = clock polarity, CPHA = clock phase.</span> PREFETCH <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">positive</span> <span style="color: #333333">:=</span> <span style="color: #0000DD; font-weight: bold">1</span>; <span style="color: #888888">-- prefetch lookahead cycles</span> SPI_2X_CLK_DIV <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">positive</span> <span style="color: #333333">:=</span> <span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #888888">-- for a 100MHz sclk_i, yields a 10MHz SCK</span> );
<span style="color: #008800; font-weight: bold">END</span> <span style="color: #BB0066; font-weight: bold">spi_loopback_test</span>;

<span style="color: #008800; font-weight: bold">ARCHITECTURE</span> <span style="color: #BB0066; font-weight: bold">behavior</span> <span style="color: #008800; font-weight: bold">OF</span> <span style="color: #BB0066; font-weight: bold">spi_loopback_test</span> <span style="color: #008800; font-weight: bold">IS</span>

<span style="color: #333333">--=========================================================</span>
<span style="color: #888888">-- Component declaration for the Unit Under Test (UUT)</span>
<span style="color: #333333">--=========================================================</span>

<span style="color: #008800; font-weight: bold">COMPONENT</span> <span style="color: #BB0066; font-weight: bold">spi_loopback</span>
<span style="color: #008800; font-weight: bold">PORT</span>(
	m_clk_i <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">IN</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	m_rst_i <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">IN</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	m_spi_miso_i <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">IN</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	m_di_i <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">IN</span> <span style="color: #333399; font-weight: bold">std_logic_vector</span>(N<span style="color: #333333">-</span><span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>);
	m_wren_i <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">IN</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	s_clk_i <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">IN</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	s_spi_ssel_i <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">IN</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	s_spi_sck_i <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">IN</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	s_spi_mosi_i <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">IN</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	s_di_i <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">IN</span> <span style="color: #333399; font-weight: bold">std_logic_vector</span>(N<span style="color: #333333">-</span><span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>);
	s_wren_i <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">IN</span> <span style="color: #333399; font-weight: bold">std_logic</span>;          
	m_spi_ssel_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	m_spi_sck_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	m_spi_mosi_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	m_di_req_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	m_do_valid_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	m_do_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic_vector</span>(N<span style="color: #333333">-</span><span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>);
	m_do_transfer_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	m_wren_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	<span style="color: #888888">-- m_wren_ack_o : OUT std_logic;</span>
	m_rx_bit_reg_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	m_state_dbg_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic_vector</span>(<span style="color: #0000DD; font-weight: bold">5</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>);
	m_core_clk_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	m_core_n_clk_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	m_sh_reg_dbg_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic_vector</span>(N<span style="color: #333333">-</span><span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>);
	s_spi_miso_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	s_di_req_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	s_do_valid_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	s_do_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic_vector</span>(N<span style="color: #333333">-</span><span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>);
	s_do_transfer_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	s_wren_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
	<span style="color: #888888">-- s_wren_ack_o : OUT std_logic;</span>
	<span style="color: #888888">-- s_rx_bit_reg_o : OUT std_logic;</span>
	s_state_dbg_o <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">OUT</span> <span style="color: #333399; font-weight: bold">std_logic_vector</span>(<span style="color: #0000DD; font-weight: bold">5</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>)
	);
<span style="color: #008800; font-weight: bold">END</span> <span style="color: #008800; font-weight: bold">COMPONENT</span>;

<span style="color: #333333">--=========================================================</span>
<span style="color: #888888">-- constants</span>
<span style="color: #333333">--=========================================================</span>
<span style="color: #008800; font-weight: bold">constant</span> fifo_memory_size <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">integer</span> <span style="color: #333333">:=</span> <span style="color: #0000DD; font-weight: bold">16</span>;
<span style="color: #008800; font-weight: bold">shared</span> <span style="color: #008800; font-weight: bold">variable</span> ENDSIM <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">boolean</span>;

<span style="color: #333333">--=========================================================</span>
<span style="color: #888888">-- types</span>
<span style="color: #333333">--=========================================================</span>
<span style="color: #008800; font-weight: bold">type</span> fifo_memory_type <span style="color: #008800; font-weight: bold">is</span> <span style="color: #008800; font-weight: bold">array</span> (<span style="color: #0000DD; font-weight: bold">0</span> <span style="color: #008800; font-weight: bold">to</span> fifo_memory_size<span style="color: #333333">-</span><span style="color: #0000DD; font-weight: bold">1</span>) <span style="color: #008800; font-weight: bold">of</span> <span style="color: #333399; font-weight: bold">std_logic_vector</span> (<span style="color: #0000DD; font-weight: bold">31</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>);

<span style="color: #333333">--=========================================================</span>
<span style="color: #888888">-- signals to connect the instances</span>
<span style="color: #333333">--=========================================================</span>
<span style="color: #888888">-- internal clk and rst</span>
<span style="color: #008800; font-weight: bold">signal</span> m_clk <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span> <span style="color: #333333">:=</span> <span style="color: #0044DD">&#39;0&#39;</span>;                <span style="color: #888888">-- clock domain for the master parallel interface. Must be faster than spi bus sck.</span>
<span style="color: #008800; font-weight: bold">signal</span> s_clk <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span> <span style="color: #333333">:=</span> <span style="color: #0044DD">&#39;0&#39;</span>;                <span style="color: #888888">-- clock domain for the slave parallel interface. Must be faster than spi bus sck.</span>
<span style="color: #008800; font-weight: bold">signal</span> rst <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span> <span style="color: #333333">:=</span> <span style="color: #0044DD">&#39;U&#39;</span>;
<span style="color: #888888">-- spi bus wires</span>
<span style="color: #008800; font-weight: bold">signal</span> spi_sck <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
<span style="color: #008800; font-weight: bold">signal</span> spi_ssel <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
<span style="color: #008800; font-weight: bold">signal</span> spi_miso <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
<span style="color: #008800; font-weight: bold">signal</span> spi_mosi <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
<span style="color: #888888">-- master parallel interface</span>
<span style="color: #008800; font-weight: bold">signal</span> di_m <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic_vector</span> (N<span style="color: #333333">-</span><span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>) <span style="color: #333333">:=</span> (<span style="color: #008800; font-weight: bold">others</span> <span style="color: #333333">=&gt;</span> <span style="color: #0044DD">&#39;0&#39;</span>);
<span style="color: #008800; font-weight: bold">signal</span> do_m <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic_vector</span> (N<span style="color: #333333">-</span><span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>) <span style="color: #333333">:=</span> (<span style="color: #008800; font-weight: bold">others</span> <span style="color: #333333">=&gt;</span> <span style="color: #0044DD">&#39;U&#39;</span>);
<span style="color: #008800; font-weight: bold">signal</span> do_valid_m <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
<span style="color: #008800; font-weight: bold">signal</span> do_transfer_m <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
<span style="color: #008800; font-weight: bold">signal</span> di_req_m <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
<span style="color: #008800; font-weight: bold">signal</span> wren_m <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span> <span style="color: #333333">:=</span> <span style="color: #0044DD">&#39;0&#39;</span>;
<span style="color: #008800; font-weight: bold">signal</span> wren_o_m <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span> <span style="color: #333333">:=</span> <span style="color: #0044DD">&#39;U&#39;</span>;
<span style="color: #888888">-- signal wren_ack_o_m : std_logic := &#39;U&#39;;</span>
<span style="color: #008800; font-weight: bold">signal</span> rx_bit_reg_m <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
<span style="color: #008800; font-weight: bold">signal</span> state_m <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic_vector</span> (<span style="color: #0000DD; font-weight: bold">5</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>);
<span style="color: #008800; font-weight: bold">signal</span> core_clk_o_m <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
<span style="color: #008800; font-weight: bold">signal</span> core_n_clk_o_m <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
<span style="color: #008800; font-weight: bold">signal</span> sh_reg_m <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic_vector</span> (N<span style="color: #333333">-</span><span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>) <span style="color: #333333">:=</span> (<span style="color: #008800; font-weight: bold">others</span> <span style="color: #333333">=&gt;</span> <span style="color: #0044DD">&#39;0&#39;</span>);
<span style="color: #888888">-- slave parallel interface</span>
<span style="color: #008800; font-weight: bold">signal</span> di_s <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic_vector</span> (N<span style="color: #333333">-</span><span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>) <span style="color: #333333">:=</span> (<span style="color: #008800; font-weight: bold">others</span> <span style="color: #333333">=&gt;</span> <span style="color: #0044DD">&#39;0&#39;</span>);
<span style="color: #008800; font-weight: bold">signal</span> do_s <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic_vector</span> (N<span style="color: #333333">-</span><span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>);
<span style="color: #008800; font-weight: bold">signal</span> do_valid_s <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
<span style="color: #008800; font-weight: bold">signal</span> do_transfer_s <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
<span style="color: #008800; font-weight: bold">signal</span> di_req_s <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span>;
<span style="color: #008800; font-weight: bold">signal</span> wren_s <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span> <span style="color: #333333">:=</span> <span style="color: #0044DD">&#39;0&#39;</span>;
<span style="color: #008800; font-weight: bold">signal</span> wren_o_s <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic</span> <span style="color: #333333">:=</span> <span style="color: #0044DD">&#39;U&#39;</span>;
<span style="color: #888888">-- signal wren_ack_o_s : std_logic := &#39;U&#39;;</span>
<span style="color: #888888">-- signal rx_bit_reg_s : std_logic;</span>
<span style="color: #008800; font-weight: bold">signal</span> state_s <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic_vector</span> (<span style="color: #0000DD; font-weight: bold">5</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>);
<span style="color: #888888">-- signal sh_reg_s : std_logic_vector (N-1 downto 0);</span>

<span style="color: #333333">--=========================================================</span>
<span style="color: #888888">-- Clock period definitions</span>
<span style="color: #333333">--=========================================================</span>
<span style="color: #008800; font-weight: bold">constant</span> m_clk_period <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">time</span> <span style="color: #333333">:=</span> <span style="color: #0000DD; font-weight: bold">11</span> ns;          <span style="color: #888888">-- 100MHz master parallel clock</span>
<span style="color: #008800; font-weight: bold">constant</span> s_clk_period <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">time</span> <span style="color: #333333">:=</span>  <span style="color: #0000DD; font-weight: bold">9</span> ns;          <span style="color: #888888">-- 100MHz slave parallel clock</span>

<span style="color: #008800; font-weight: bold">BEGIN</span>

<span style="color: #333333">--=========================================================</span>
<span style="color: #888888">-- Component instantiation for the Unit Under Test (UUT)</span>
<span style="color: #333333">--=========================================================</span>

Inst_spi_loopback<span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">entity</span> <span style="color: #BB0066; font-weight: bold">work</span>.spi_loopback(Structural)
     <span style="color: #008800; font-weight: bold">generic</span> <span style="color: #008800; font-weight: bold">map</span> (N <span style="color: #333333">=&gt;</span> N, CPOL <span style="color: #333333">=&gt;</span> CPOL, CPHA <span style="color: #333333">=&gt;</span> CPHA, PREFETCH <span style="color: #333333">=&gt;</span> PREFETCH, SPI_2X_CLK_DIV <span style="color: #333333">=&gt;</span> SPI_2X_CLK_DIV)

<span style="color: #888888">-- Inst_spi_loopback: spi_loopback</span> <span style="color: #008800; font-weight: bold">port</span> <span style="color: #008800; font-weight: bold">map</span>( <span style="color: #888888">----------------MASTER-----------------------</span> m_clk_i <span style="color: #333333">=></span> m_clk, m_rst_i <span style="color: #333333">=></span> rst, m_spi_ssel_o <span style="color: #333333">=></span> spi_ssel, m_spi_sck_o <span style="color: #333333">=></span> spi_sck, m_spi_mosi_o <span style="color: #333333">=></span> spi_mosi, m_spi_miso_i <span style="color: #333333">=></span> spi_miso, m_di_req_o <span style="color: #333333">=></span> di_req_m, m_di_i <span style="color: #333333">=></span> di_m, m_wren_i <span style="color: #333333">=></span> wren_m, m_do_valid_o <span style="color: #333333">=></span> do_valid_m, m_do_o <span style="color: #333333">=></span> do_m, <span style="color: #888888">----- debug -----</span> m_do_transfer_o <span style="color: #333333">=></span> do_transfer_m, m_wren_o <span style="color: #333333">=></span> wren_o_m, <span style="color: #888888">-- m_wren_ack_o => wren_ack_o_m,</span> m_rx_bit_reg_o <span style="color: #333333">=></span> rx_bit_reg_m, <span style="color: #888888">-- m_state_dbg_o => state_m,</span> m_core_clk_o <span style="color: #333333">=></span> core_clk_o_m, m_core_n_clk_o <span style="color: #333333">=></span> core_n_clk_o_m, m_sh_reg_dbg_o <span style="color: #333333">=></span> sh_reg_m, <span style="color: #888888">----------------SLAVE-----------------------</span> s_clk_i <span style="color: #333333">=></span> s_clk, s_spi_ssel_i <span style="color: #333333">=></span> spi_ssel, s_spi_sck_i <span style="color: #333333">=></span> spi_sck, s_spi_mosi_i <span style="color: #333333">=></span> spi_mosi, s_spi_miso_o <span style="color: #333333">=></span> spi_miso, s_di_req_o <span style="color: #333333">=></span> di_req_s, s_di_i <span style="color: #333333">=></span> di_s, s_wren_i <span style="color: #333333">=></span> wren_s, s_do_valid_o <span style="color: #333333">=></span> do_valid_s, s_do_o <span style="color: #333333">=></span> do_s, <span style="color: #888888">----- debug -----</span> s_do_transfer_o <span style="color: #333333">=></span> do_transfer_s, s_wren_o <span style="color: #333333">=></span> wren_o_s <span style="color: #888888">-- s_wren_ack_o => wren_ack_o_s</span> <span style="color: #888888">-- s_rx_bit_reg_o => rx_bit_reg_s</span> <span style="color: #888888">-- s_state_dbg_o => state_s</span> <span style="color: #888888">-- s_sh_reg_dbg_o => sh_reg_s</span> );

<span style="color: #333333">--=========================================================</span>
<span style="color: #888888">-- Clock generator processes</span>
<span style="color: #333333">--=========================================================</span>
m_clk_process <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">process</span>
<span style="color: #008800; font-weight: bold">begin</span>
    <span style="color: #008800; font-weight: bold">if</span> ENDSIM<span style="color: #333333">=</span>false <span style="color: #008800; font-weight: bold">then</span>
        m_clk <span style="color: #333333">&lt;=</span> <span style="color: #0044DD">&#39;0&#39;</span>;
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">for</span> m_clk_period<span style="color: #333333">/</span><span style="color: #0000DD; font-weight: bold">2</span>;
        m_clk <span style="color: #333333">&lt;=</span> <span style="color: #0044DD">&#39;1&#39;</span>;
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">for</span> m_clk_period<span style="color: #333333">/</span><span style="color: #0000DD; font-weight: bold">2</span>;
    <span style="color: #008800; font-weight: bold">else</span>
        <span style="color: #008800; font-weight: bold">wait</span>;
    <span style="color: #008800; font-weight: bold">end</span> <span style="color: #008800; font-weight: bold">if</span>;
<span style="color: #008800; font-weight: bold">end</span> <span style="color: #008800; font-weight: bold">process</span> <span style="color: #BB0066; font-weight: bold">m_clk_process</span>;

s_clk_process <span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">process</span>
<span style="color: #008800; font-weight: bold">begin</span>
    <span style="color: #008800; font-weight: bold">if</span> ENDSIM<span style="color: #333333">=</span>false <span style="color: #008800; font-weight: bold">then</span>
        s_clk <span style="color: #333333">&lt;=</span> <span style="color: #0044DD">&#39;0&#39;</span>;
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">for</span> s_clk_period<span style="color: #333333">/</span><span style="color: #0000DD; font-weight: bold">2</span>;
        s_clk <span style="color: #333333">&lt;=</span> <span style="color: #0044DD">&#39;1&#39;</span>;
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">for</span> s_clk_period<span style="color: #333333">/</span><span style="color: #0000DD; font-weight: bold">2</span>;
    <span style="color: #008800; font-weight: bold">else</span>
        <span style="color: #008800; font-weight: bold">wait</span>;
    <span style="color: #008800; font-weight: bold">end</span> <span style="color: #008800; font-weight: bold">if</span>;
<span style="color: #008800; font-weight: bold">end</span> <span style="color: #008800; font-weight: bold">process</span> <span style="color: #BB0066; font-weight: bold">s_clk_process</span>;

<span style="color: #333333">--=========================================================</span>
<span style="color: #888888">-- rst_i process</span>
<span style="color: #333333">--=========================================================</span>
rst <span style="color: #333333">&lt;=</span> <span style="color: #0044DD">&#39;0&#39;</span>, <span style="color: #0044DD">&#39;1&#39;</span> <span style="color: #008800; font-weight: bold">after</span> <span style="color: #0000DD; font-weight: bold">20</span> ns, <span style="color: #0044DD">&#39;0&#39;</span> <span style="color: #008800; font-weight: bold">after</span> <span style="color: #0000DD; font-weight: bold">100</span> ns; <span style="color: #888888">-- Error: High or Low active Reset?!</span>


<span style="color: #333333">--=========================================================</span>
<span style="color: #888888">-- Master interface process</span>
<span style="color: #333333">--=========================================================</span>
master_tx_fifo_proc<span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">process</span> <span style="color: #008800; font-weight: bold">is</span>
    <span style="color: #008800; font-weight: bold">variable</span> fifo_memory <span style="color: #333333">:</span> fifo_memory_type <span style="color: #333333">:=</span> 
        (X<span style="background-color: #fff0f0">&quot;87654321&quot;,X&quot;abcdef01&quot;,X&quot;faceb007&quot;,X&quot;10203049&quot;,X&quot;85a5a5a5&quot;,X&quot;7aaa5551&quot;,X&quot;7adecabe&quot;,X&quot;57564789&quot;</span>,
         X<span style="background-color: #fff0f0">&quot;12345678&quot;,X&quot;beefbeef&quot;,X&quot;fee1600d&quot;,X&quot;f158ba17&quot;,X&quot;5ee1a7e3&quot;,X&quot;101096da&quot;,X&quot;600ddeed&quot;,X&quot;deaddead&quot;</span>);
    <span style="color: #008800; font-weight: bold">variable</span> fifo_head <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">integer</span> <span style="color: #008800; font-weight: bold">range</span> <span style="color: #0000DD; font-weight: bold">0</span> <span style="color: #008800; font-weight: bold">to</span> fifo_memory_size<span style="color: #333333">-</span><span style="color: #0000DD; font-weight: bold">1</span>;
    <span style="color: #008800; font-weight: bold">variable</span> mapping <span style="color: #333333">:</span> <span style="color: #333399; font-weight: bold">std_logic_vector</span> (<span style="color: #0000DD; font-weight: bold">31</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>);
<span style="color: #008800; font-weight: bold">begin</span>
    <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;
    di_m <span style="color: #333333">&lt;=</span> (<span style="color: #008800; font-weight: bold">others</span> <span style="color: #333333">=&gt;</span> <span style="color: #0044DD">&#39;0&#39;</span>);
    wren_m <span style="color: #333333">&lt;=</span> <span style="color: #0044DD">&#39;0&#39;</span>;
    fifo_head <span style="color: #333333">:=</span> <span style="color: #0000DD; font-weight: bold">0</span>;
    <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> rst <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;
    <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> rst <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;0&#39;</span>;
    <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;             <span style="color: #888888">-- </span>
    <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;             <span style="color: #888888">-- </span>
    <span style="color: #888888">-- Error: Master output di_req_o is not sensitive for reset: wait until di_req_m = &#39;1&#39;; -- wait shift register request for data</span>
    <span style="color: #008800; font-weight: bold">for</span> cnt <span style="color: #008800; font-weight: bold">in</span> <span style="color: #0000DD; font-weight: bold">0</span> <span style="color: #008800; font-weight: bold">to</span> (fifo_memory_size<span style="color: #333333">/</span><span style="color: #0000DD; font-weight: bold">2</span>)<span style="color: #333333">-</span><span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #008800; font-weight: bold">loop</span>
        fifo_head <span style="color: #333333">:=</span> cnt;                               <span style="color: #888888">-- pre-compute next pointer </span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        mapping <span style="color: #333333">:=</span> fifo_memory(fifo_head);              <span style="color: #888888">-- place data into tx_data input bus</span>
        di_m <span style="color: #333333">&lt;=</span> mapping(N<span style="color: #333333">-</span><span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>);                  <span style="color: #888888">-- place data into tx_data input bus</span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        wren_m <span style="color: #333333">&lt;=</span> <span style="color: #0044DD">&#39;1&#39;</span>;                                  <span style="color: #888888">-- write data into spi master</span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        wren_m <span style="color: #333333">&lt;=</span> <span style="color: #0044DD">&#39;0&#39;</span>;                                  <span style="color: #888888">-- remove write enable signal</span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> di_req_m <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;                      <span style="color: #888888">-- wait shift register request for data</span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- bigger break to see single byte transmission</span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
    <span style="color: #008800; font-weight: bold">end</span> <span style="color: #008800; font-weight: bold">loop</span>;
    
    <span style="color: #888888">-- same error again: wait until spi_ssel = &#39;1&#39;;</span>
    <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">for</span> <span style="color: #0000DD; font-weight: bold">1000</span> ns;
    <span style="color: #008800; font-weight: bold">for</span> cnt <span style="color: #008800; font-weight: bold">in</span> (fifo_memory_size<span style="color: #333333">/</span><span style="color: #0000DD; font-weight: bold">2</span>) <span style="color: #008800; font-weight: bold">to</span> fifo_memory_size<span style="color: #333333">-</span><span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #008800; font-weight: bold">loop</span>
        fifo_head <span style="color: #333333">:=</span> cnt;                               <span style="color: #888888">-- pre-compute next pointer </span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        mapping <span style="color: #333333">:=</span> fifo_memory(fifo_head);              <span style="color: #888888">-- place data into tx_data input bus</span>
        di_m <span style="color: #333333">&lt;=</span> mapping(N<span style="color: #333333">-</span><span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #008800; font-weight: bold">downto</span> <span style="color: #0000DD; font-weight: bold">0</span>);                  <span style="color: #888888">-- place data into tx_data input bus</span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        wren_m <span style="color: #333333">&lt;=</span> <span style="color: #0044DD">&#39;1&#39;</span>;                                  <span style="color: #888888">-- write data into spi master</span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> m_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> m_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        wren_m <span style="color: #333333">&lt;=</span> <span style="color: #0044DD">&#39;0&#39;</span>;                                  <span style="color: #888888">-- remove write enable signal</span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> di_req_m <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;                      <span style="color: #888888">-- wait shift register request for data</span>
    <span style="color: #008800; font-weight: bold">end</span> <span style="color: #008800; font-weight: bold">loop</span>;
    
    <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">for</span> <span style="color: #0000DD; font-weight: bold">1000</span> ns;
    ENDSIM <span style="color: #333333">:=</span> true;
    <span style="color: #008800; font-weight: bold">wait</span>;
<span style="color: #008800; font-weight: bold">end</span> <span style="color: #008800; font-weight: bold">process</span> <span style="color: #BB0066; font-weight: bold">master_tx_fifo_proc</span>;


<span style="color: #333333">--=========================================================</span>
<span style="color: #888888">-- Slave interface process</span>
<span style="color: #333333">--=========================================================</span>
di_s <span style="color: #333333">&lt;=</span> do_s;                                           <span style="color: #888888">-- loop data from output to input</span>

slave_tx_fifo_proc<span style="color: #333333">:</span> <span style="color: #008800; font-weight: bold">process</span> <span style="color: #008800; font-weight: bold">is</span>
<span style="color: #008800; font-weight: bold">begin</span>
    wren_s <span style="color: #333333">&lt;=</span> <span style="color: #0044DD">&#39;0&#39;</span>;
    <span style="color: #008800; font-weight: bold">while</span> <span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #333333">=</span> <span style="color: #0000DD; font-weight: bold">1</span> <span style="color: #008800; font-weight: bold">loop</span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> di_req_s <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;                      <span style="color: #888888">-- wait shift register request for data</span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> s_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> s_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> s_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> s_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        wren_s <span style="color: #333333">&lt;=</span> <span style="color: #0044DD">&#39;1&#39;</span>;                                  <span style="color: #888888">-- write data into shift register</span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> s_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> s_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        <span style="color: #008800; font-weight: bold">wait</span> <span style="color: #008800; font-weight: bold">until</span> s_clk<span style="color: #0000CC">&#39;event</span> <span style="color: #008800; font-weight: bold">and</span> s_clk <span style="color: #333333">=</span> <span style="color: #0044DD">&#39;1&#39;</span>;         <span style="color: #888888">-- </span>
        wren_s <span style="color: #333333">&lt;=</span> <span style="color: #0044DD">&#39;0&#39;</span>;                                  <span style="color: #888888">-- remove write enable signal</span>
    <span style="color: #008800; font-weight: bold">end</span> <span style="color: #008800; font-weight: bold">loop</span>;
    <span style="color: #008800; font-weight: bold">wait</span>;
<span style="color: #008800; font-weight: bold">end</span> <span style="color: #008800; font-weight: bold">process</span> <span style="color: #BB0066; font-weight: bold">slave_tx_fifo_proc</span>;

<span style="color: #008800; font-weight: bold">END</span> <span style="color: #008800; font-weight: bold">ARCHITECTURE</span> <span style="color: #BB0066; font-weight: bold">behavior</span>;

</pre></div>
jdoin was assigned about 3 years ago
jdoin commented about 3 years ago

Thank you @Elias Kögel!

I will update the testbench and add a verification testbench that I use internally in production.

Thank you for the contribution.

  • Jonny Doin